使用共用電阻層在三維積體電路做垂直訊號傳輸

Abstract

本篇論文針對先前本實驗室提出的一個新型三維積體電路晶片間連接的應用架構，做出一個適合的傳輸與接收器。傳輸端的設計中，我們採用雙NMOS電晶體降低訊號擺幅，進而降低功耗以及提升操作速度。接收端的設計中，雙迴路的架構用以補償在通道輸出端不足夠的電壓擺幅，藉此提升電路之操作速度。共用電阻層傳送晶片間多重信號機制操作在1.25 Gbps時能達到0.16 pJ/bit能量效率，使用台積電 0.18微米1P6M CMOS 製程來實現與驗證此新型的三維晶片傳輸架構。

This thesis proposes a die-to-die communication mechanism. Its transmitting medium is a common-resistive layer. In the transmitter design, to boost the operating speed and reduce leakage power originated from the neighboring pads, a dual-NMOS driver is used. In the receiver design, to compensate for the insufficient voltage level in the channel-output node when the circuit is operated at high speed, a double-feedback compensating mechanism is adopted. This interconnect has energy efficiency of 0.16 pJ/bit at 1.25 Gbps. The proposed vertical signal transmission method is simulated in TSMC 0.18-um process for demonstration of the architecture.