CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	CHEN, MJ	en_US
dc.contributor.author	WU, CY	en_US
dc.date.accessioned	2014-12-08T15:06:09Z	-
dc.date.available	2014-12-08T15:06:09Z	-
dc.date.issued	1986-10-01	en_US
dc.identifier.issn	0038-1101	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4721	-
dc.language.iso	en_US	en_US
dc.title	CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS	en_US
dc.type	Article	en_US
dc.identifier.journal	SOLID-STATE ELECTRONICS	en_US
dc.citation.volume	29	en_US
dc.citation.issue	10	en_US
dc.citation.spage	1079	en_US
dc.citation.epage	1086	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	工學院	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	College of Engineering	en_US
dc.identifier.wosnumber	WOS:A1986E469700011	-
dc.citation.woscount	0	-
顯示於類別：	期刊論文