| 標題: | IMPROVED SYSTOLIC ARRAY FOR LINEAR DISCRIMINANT FUNCTION CLASSIFIER |
| 作者: | WANG, CL WEI, CH CHEN, SH 傳播研究所 電控工程研究所 Institute of Communication Studies Institute of Electrical and Control Engineering |
| 公開日期: | 16-Jan-1986 |
| URI: | http://hdl.handle.net/11536/4770 |
| ISSN: | 0013-5194 |
| 期刊: | ELECTRONICS LETTERS |
| Volume: | 22 |
| Issue: | 2 |
| 起始頁: | 85 |
| 結束頁: | 86 |
| Appears in Collections: | Articles |
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- EFFICIENT BIT-LEVEL SYSTOLIC ARRAY FOR THE LINEAR DISCRIMINANT FUNCTION CLASSIFIER / WANG, CL;WEI, CH;CHEN, SH
- EFFICIENT BIT-LEVEL SYSTOLIC ARRAY IMPLEMENTATION OF FIR AND IIR DIGITAL-FILTERS / WANG, CL;WEI, CH;CHEN, SH
- RESIDUE SYSTOLIC IMPLEMENTATIONS FOR NEURAL NETWORKS / ZHANG, CN;WANG, M;TSENG, CC
- A systolic algorithm for solving dense linear systems / Lin, CJ
- REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY / WANG, JJ;JEN, CW
- DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYS / JEN, CW;KWAI, DM
- ON EQUIVALENT SYSTOLIC DESIGNS OF LU DECOMPOSITION AND ITS ALGEBRAIC REPRESENTATION / HOU, YC;TSAY, JC
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