非晶矽薄膜於電阻式記憶體研究

Abstract

近年來電阻式記憶體因具有單位元件體積小(可提高密度)、低操作電壓、低耗能、結構簡單、非破壞性讀取、快速操作、資料儲存時間長及重複操作可靠度佳等潛力而被廣泛的研究。 本篇論文中，我們製備出與CMOS 製程匹配的Cu/a-Si/p++Si元件，利用安捷倫4155及4156電性量測分析元件，針對其轉換機制與記憶體特性的表現作討論。元件在高溫(85℃)環境下穩定性良好，可以維持超過10^4秒而不衰減，且高低電阻態比例可以達到10^6以上，在眾多材料中表現優異，再加上銅電極及非晶矽轉換層和CMOS製程相容性高，在未來製程整合上遇到的問題阻力也相對較小。 另外、本研究也提出元件的電阻轉換現象，是由固定的金屬區域及變動的燈絲(Filament)路徑組成導通路徑，上電極銅在初始形成過程(Forming Process)擴散進入a-Si形成金屬區域，使得電流達到限制電流，而尚未形成金屬區域的小部份非晶矽，則藉由單根燈絲路徑的形成及破壞來達到高低電阻態之間的轉換，低電阻態時導通電流會受到燈絲形狀改變而影響，電流電壓曲線受到溫度影響小，電流傳導機制為穿隧(Tunneling)；而在高電阻態則受到非晶矽薄膜的缺陷影響是空間電荷限制電流(SCLC)傳導機制，並利用WKB近似估算出電阻轉換層厚度約5奈米左右，並且不受非晶矽薄膜總厚度的影響。

The advantages of resistive random access memory, including small cell size (high-density integration), low operate voltage, low power consumption, simple structure, non-destructive reading, high speed operation, good endurance and data retention, has attracted a lot of research works recently. In this thesis, Cu/amorphous silicon (a-Si)/p++Si structures with 30nm thickness resistive switching layer was prepared and studied. The transport behaviors of Cu/ a-Si/p++Si device showed SCLC mechanism in low voltage region (-0.5~-3V) and Schottky mechanism in high voltage region (-3~-6V) during high-resistance state (HRS). The current-voltage (I-V) curves of devices were symmetric and linear in low-resistance state (LRS), which was attributed from the tunneling conduction. The diffusion of Cu atoms into a-Si film forms a large volume metallic region during forming process. And, switching between LHS and HRS was determined by the formation of metal filament with an estimated 5-nm length during program and erase. The devices showed bipolar resistive switching behaviors and exhibits an On-off ratio up to ca. 10^6. The data retention extended up to 10^4 s even at a temperature of 85℃.