可支援光線追蹤技術之可程式化高能源效率頂點處理器之設計與實現

Abstract

在本篇論文中，我們提出了一個可支援追蹤光線追蹤技術之可程式化高能源效率頂點處理器架構。所提出的頂點著色器採用了以下四項技術分別是： 1) 可供最多四項資料流浮點數運算路徑之超長指令，2) 多層級的Pre-TnL頂點快取記憶體與完全關聯式之Post-TnL頂點快取記憶體，3) 可支援Whitted-style光線追蹤技術，4) 背面多邊形切除與光線三角形交集測試雙元件之硬體資源共享。 本論文提出的頂點處理晶片採用TSMC 90奈米製程，對於無頂點打光與有頂點打光其頂點輸出率分別為4.5Mvertices/s 與100Mvertices/s。且可提供高能源效率處理達268.33Kvertices/mJ。

In this work, an energy-efficient programmable vertex processor with ray-tracing acceleration is proposed. The proposed vertex processor architecture has four features: 1) four-issue floating-point VLIW datapath; 2) multilevel pre-TnL and post-TnL vertex cache functions; 3) Whitted-style ray-tracing supported; 4) hardware sharing between the intersection and back-face culling processing. From the chip implementation result in TSMC 90nm CMOS process technology, the operating frequency can be up to 100MHz. The post-layout simulation indicates that the vertex fill rate with and without lighting can achieve 4.5Mvertices/s and 100Mvertices/s, respectively. The resulting power efficiency is 268.33Kvertices/mJ.