具有交錯型遲滯延遲元件的低功耗數位控制振盪器

Abstract

隨著晶片製程技術的進步,可攜式產品變得越來越熱門。在可攜式產品應用中功耗就變成很重要的問題。全數位鎖相迴路在通訊系統中應用很廣。在全數位鎖相迴路電路裡，數位控制振盪器是一個關鍵性的元件。數位控制振盪器的操作頻率和靈敏度可以影響整個全數位鎖相迴路的性能，不只如此，功耗的比例是全數位鎖相迴路50%以上。設計一個低功耗的全數位鎖相迴路，降低數位控制振盪器的功耗是一個非常有效率的方法。 本論文將會提出一個具有低功耗的新型延遲元件。這個交錯型遲滯延遲元件可以節省電源，達到低功耗，小面積和高效能。數位控制振盪器架構採用串聯和改良型二權重式架構，但是這個架構會延生出一些問題，例如最快頻率限制和突波(glitch)問題。這些問題在本論文中會被一一解決。我們使用標準元件庫來設計整個晶片，並利用合成軟體及自動佈局工具實現電路，最後以90奈米1P9M標準CMOS製程來完成晶片。 本論文提出的交錯型遲滯延遲元件和標準元件(AND gate)相比可節省87%的功耗，本論文提出的數位振盪器為480MHz，功率消耗為128uW。

As technology advances, portable devices become more and more popular. In portable devices, the power consumption becomes an important design issue. An all digital phase lock loop (ADPLL) has been widely used in frequency synthesizer and communication systems. Digitally controlled oscillator (DCO) is the key component of performance and power of ADPLLs. The operated range and delay resolution of the DCO dominate jitter and output range of an ADPLL. A DCO occupies over 50% power consumption of an ADPLL. Power reduction on a DCO can effectively cut down the overall ADPLL power. This work proposes a novel delay cell in low power applications. The interlaced hysteresis delay cell has low power consumption, small area and high quality. The DCO structure uses the modified binary-weighted delay stage and cascade-stage structure. However, the disadvantages of the structure are the serious glitches and the limited fastest frequency. The proposed solution uses a synchronization cell to avoid glitches. Moreover, the proposed DCO also increases the fastest frequency. This chip is implemented with standard cell library by synthesis and auto place-and-route tools. The low power DCO is fabricated in 90nm 1P9M standard CMOS process. The proposed IHDC reduces over 87% power consumption on the standard DCO which is based on AND gates. The power consumption of the proposed DCO is 128uW at 480MHz.