鰭狀及三閘極場效電晶體元件、邏輯電路、類比電路和靜態隨機存取記憶體之研究與分析

Abstract

本篇論文探討和綜合比較鰭狀(FinFET)及三閘極(Trigate)場效電晶體在數位邏輯電路(Logic circuits)、靜態隨機存取記憶體(SRAM)穩定度和維德拉電流源(Widlar Current Source)之研究和分析。在關鍵本質參數變異部分，我們使用3D數值模擬軟體考慮了鰭線邊緣粗糙度（fin Line Edge Roughness），功函數變異程度（Work Function Variation）與單一電荷造成的隨機電報雜訊（Random Telegraph Noise）在鰭狀與三閘極先進場效電晶體上的影響與討論。

在同時考慮線邊緣粗糙度和功函數變異程度以及基於相同的元件寬度和鰭寬度(10nm and 7nm)的比較基準下，三閘極場效電晶體的次臨界斜率(Subthreshold Slope)、臨界電壓(VT)和靜態隨機存取記憶體穩定度較不受元件變異的影響。但在隨機電報雜訊(RTN)方面，三閘極場效電晶體因為電流分布較集中於通道底部，當電荷陷阱放置在底部時會造成較大的電流變異。因此，當我們同時考慮鰭線邊緣粗糙度和功函數變異程度的情況下，三閘極場效電晶體表現出更廣的分布、更強電荷陷阱的位置依賴性以及在元件電流、臨界電壓和互導參數(gm)受到更大的影響。 我們也研究隨機電報雜訊在靜態隨機存取記憶體穩定度、維德拉電流源、邏輯電路(Inverter、NAND和Multiplexer)的漏電流和延遲的影響。我們發現隨著操作電壓的下降，隨機電報雜訊的影響隨之增加；和鰭狀場效電晶體相比，三閘極元件為基礎的電路特性將會受到較為嚴重的影響。

In this thesis, we present a comprehensive comparative analysis of FinFET and Trigate in terms of device characteristics, stability of 6T SRAM cell, logic circuits and Widlar current source. The critical intrinsic random variations, including fin Line Edge Roughness (fin LER), Work Function Variation (WFV) and single-trap-induced Random Telegraph Noise (RTN) on FinFET and Trigate devices are investigated and compared using 3D TCAD atomistic simulations.

The results indicate that Trigate device shows slightly better variability immunity in Subthreshold Slope (S.S.), threshold voltage (VT), 6T SRAM cell stability with identical electrical width and fin width (10nm and 7nm) considering fin LER and WFV simultaneously. While considering the impact of RTN, Trigate device, with larger fraction of electron current near the bottom region of the silicon fin channel, suffers larger RTN degradation for the trap located at the bottom region, whereas less impact is observed with single charged trap at the top region. As such, Trigate device exhibits broader dispersion and stronger dependence on the trap location. In the presence of fin LER and WFV, larger impact is found in RTN amplitude (ΔID/ID), nominal Δgm/gm, σ(Δgm/gm) and ΔVT with a trap placed at the worst position of Trigate MOSFET. Furthermore, the influence of RTN on 6T SRAM cell stability, Widlar current source, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. It is observed that with degreasing supply voltage, the importance of RTN degradation increases, and that Trigate-based circuits are found to be inferior to the FinFET counterparts.