在鍺通道金氧半場效電晶體上使用後沉積氧化製造二氧化鉿/三氧化二鋁/氧化鍺/鍺之閘極介電層堆疊結構的研究

Abstract

在這篇論文之中，首先我們研究了在原子層沉積三氧化二鋁介電層之後使用後沉積氧化方式，藉由快速升溫退火爐通氧氣退火在鍺介面上形成薄的GeOx介電層之鍺P型金氧半電容。我們藉由後沉積氧化方式將等效氧化層厚度降至1.41奈米，並且使用及探討了電導法(conductance method)來萃取介面缺陷電荷密度。使用後沉積氧化方式之試片與一般直接熱成長二氧化鍺之試片比較起來有較小的介面缺陷電荷密度，而我們也研究了GeOx /Ge之介面缺陷電荷密度與GeOx厚度的關係。我們認為之所以用較高溫度的後沉積氧化方式會有較厚的GeOx介電層以及較小的介面缺陷電荷密度是因為在較高溫度下會有較大的鍺三價波峰存在。介面缺陷電荷密度再經由300度30分鐘氫氣氮氣混合之熱退火可被降低，介面缺陷電荷密度的質在熱退火後下降了16% ~ 44%。而在熱退火後我們也發現了平帶電壓往正的方向移動以及較小的電壓遲滯現象。我們最後決定選用二氧化鉿/三氧化二鋁之閘極介電層以及使用後沉積氧化方式520度3分鐘這組條件來繼續進行元件的製造。 其次，我們研究了氫氣氮氣混合之熱退火對鍺的接面以及元件特性之影響，包含了P型金氧半場效電晶體以及N型金氧半場效電晶體。在熱退火之後，我們的p+n接面以及P型金氧半場效電晶體的電流開關比分別是4 orders與1.4×103，以及較佳的次臨界擺幅(165mV/dec)；而在n+p接面以及N型金氧半場效電晶體方面，電流開關比分別是3.5 orders與2.3×103，次臨界擺幅則是151mV/dec。對P型以及N型兩者金氧半場效電晶體而言，在氫氣氮氣混合之熱退火後，源極汲極串聯阻抗上升，電洞載子遷移率提高，電洞載子遷移率波峰達到375 cm2/Vs。綜合比較300度30分鐘氫氣氮氣混合之熱退火對P型以及N型兩者金氧半場效電晶體的優缺點，在熱退火之後，平帶電壓會往正的方向移動，有較高的驅動電流，較佳的次臨界擺幅以及較高的電洞載子遷移率，然而源極汲極串聯阻抗卻會上升。 最後，我們研究了氫氣氮氣混合之熱退火對磊晶鍺在絕緣層上覆矽金氧半場效電晶體的影響，包含了磊晶60奈米鍺以及30奈米鍺在絕緣層上覆矽。對P型以及N型兩者金氧半場效電晶體而言，在熱退火之後，平帶電壓會往正的方向移動，較佳的次臨界擺幅，較高的驅動電流，較低的漏電流，較大的源極汲極串聯阻抗以及較高的電洞載子遷移率，電洞載子遷移率波峰達到313 cm2/Vs(磊晶60奈米鍺)以及194 cm2/Vs(磊晶30奈米鍺)。磊晶30奈米鍺在絕緣層上覆矽金氧半場效電晶體有較佳的次臨界擺幅，而磊晶60奈米鍺在絕緣層上覆矽金氧半場效電晶體則是有較大的驅動電流以及電洞載子遷移率。

In this thesis, firstly, germanium MOS capacitors using post deposition oxidation method to form a thin GeOx interfacial layer by oxidizing Ge surface beneath an ALD Al2O3 layer using high-k RTO was fabricated and analyzed electrically. The EOT value was scaled down to 1.41 nm by PDO. Theory of the conductance method was discussed in detail, and utilizing it to extract the interface state density. The post oxidation deposition samples have less interface state density than thermal GeO2 samples, and the Dit of GeOx/Ge MOS interface controlled by the GeOx thickness has been studied. We think the less interface state density is because of the thicker GeOx interfacial layer and larger Ge3+ peak which the higher post deposition oxidation temperature grown. Interface state density was shown to be reduced through 300°C 30 minutes forming gas annealing, the Dit value has been reduced 16% ~ 44%. The positive VFB shift and lower C-V hysteresis is shown in the samples after FGA. The HfO2/Al2O3 gate stack with PDO 520°C 3min was selected to be the best condition to fabricate Ge MOSFETs. Secondly, we investigated the effect of FGA on Ge junction and device characteristics, including both PMOSFET and NMOSFET. On/off ratio of our p+n junction and PMOSFET reached 4 orders and 1.4×103 respectively, with better subthreshold swing (165mV/dec) obtained after FGA. And on/off ratio of our n+p junction and NMOSFET reached 3.5 orders and 2.3×103 respectively, with better subthreshold swing (151mV/dec) obtained after FGA. For both PMOSFETs and NMOSFETs, the larger series resistance and higher hole mobility are observed after FGA, a peak hole mobility of 375 cm2/Vs after FGA is obtained. Pros and cons of FGA at 300°C 30 min on both PMOSFET and NMOSFET were summarized according to our experimental data. Positive VFB shift, higher drive current, better subthreshold swing and higher hole mobility are obtained after FGA, while series resistance is increased after FGA. Finally, we investigated the effect of FGA on epi-Ge on SOI MOSFETs characteristics, including epi-60nm Ge on SOI and epi-30nm Ge on SOI. For both PMOSFETs and NMOSFETs, the positive Vth shift, better subthreshold swing, higher on current, lower off current and higher RSD are obtained after FGA. Also, the higher hole mobility is observed, a peak hole mobility of 313 cm2/Vs for epi-60nm PMOSFET and 194 cm2/Vs for epi-30nm NMOSFET after FGA are obtained. Epi-30nm Ge on SOI MOSFETs have better subthreshold swing, while epi-60nm Ge on SOI MOSFETs have larger on current and higher hole mobility.