標題: 使用0.18μm互補式金氧半製程設計具雙二元自動追蹤迴路之10Gb/s 44.2dB可適性等化器
A 10-Gb/s 44.2dB Adaptive Equalizer with Automatic Duobinary Tracking Loop in 0.18μm CMOS Technology
作者: 李安修
Li, An-Siou
蔡嘉明
Tsai, Chia-Ming
電子工程學系 電子研究所
關鍵字: 可適性等化器;雙二元;adaptive equalizer;duobinary
公開日期: 2012
摘要: 本論文描述一個使用雙二元傳輸並結合即時自動雙二元追蹤技術以產生高品質的雙二元訊號,簡化資料回復過程並達到更高的資料傳輸速率的等化器,並且採用雙增益模式的方式,使得等化器能在面對訊號衰減量較大的情況時、提高增益,在面對訊號衰減量較小的情況時、節省功率消耗。另外還透過偏差消除的技術來拓展時脈相位邊限。此晶片是使用0.18μm互補式金氧半製程設計,並且能達到10Gb/s的資料傳輸率。量測結果顯示等化器在3-英吋至66-英吋的FR-4電路板通道皆可以產生品質非常好的雙二元及二元訊號,量測使用的通道分別在5GHz衰減3.6dB及44.2dB,在誤碼率小於10-12的情況下,66-英吋的FR-4電路板通道的時脈相位邊限可以達到58% UI,此等化器在1.8-V的電壓供應下,高增益模式只消耗了28.4mW之功率。
This thesis describes an adaptive equalizer using duobinary signaling scheme combined with the proposed real-time automatic duobinary tracking technique which is capable of regenerating a high-quality duobinary signal to simplify the data recovery process and achieve a higher data rate. By adopt dual-gain mode topology, the equalizer increases gain boost when signals with higher losses and saves power consumption when signals with lower losses. Moreover, the offset cancellation technique is used to broaden clock phase margin. The circuit is implemented 0.18μm CMOS technology and operates at a 10-Gb/s data rate, the measurement results show that the equalizer produces an excellent duobinary and NRZ eye performance for 3-inch to 66-inch FR-4 traces. The measured channel losses at 5GHz are 3.6dB and 44.2dB, respectively. For a bit error rate of 10-12, the obtained clock phase margin is 58% UI for 66-inch trace. The equalizer consumes only 28.4mW for high gain mode from a 1.8-V supply.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079911630
http://hdl.handle.net/11536/49159
Appears in Collections:Thesis