適用於爆模式傳輸之6Gb/s 40dB數位式控制可適性等化器

Abstract

本論文提出了適用於爆模式傳輸之可適性等化器，而爆模式傳輸已廣泛應用在許多高速串列傳輸系統，如USB 3.0 與 PCI Express Generation II，故能應用在爆模式傳輸下之等化器已變得越來越重要。有效偵測器被用來扮演著這個角色，能偵測資料是否處於爆模式傳輸，當傳輸處於閒置時，數位式可適性控制器被用來暫存先前偵測迴路鎖定時之可適性資訊，因此下一筆爆發資料傳輸時不須重新鎖定，藉由使用有效偵測器及數位式可適性控制器，爆模式傳輸之反應時間只需要5.5ns或33個位元時間。此外，傳統之加成控制的方法於全通路徑及高頻路徑上有著相位延遲不匹配的問題，且對於系統於短通道應用下，在高頻路徑上會產生龐大的過激導致訊號失真，因此不適用於高補償並具有廣範圍通道變化的應用，在此本論文提出一種管線式的可適性等化器，能根據通道衰減程度開啟不同級數的等化濾波器，因此所提出之架構亦能有較好的功率效率。此可適性等化器使用0.18μm互補式金屬氧化物半導體製程製造，並可適用於6Gb/s的資料傳輸速率，補償範圍可達90英吋的FR-4印刷電路板，而此通道在3GHz有著40dB的衰減量，系統在1.8V的電壓供應下共消耗了26.7mW功率。

This thesis presents a burst-mode equalizer for application in burst-mode communications. The burst-mode communication has been generally applied in many high speed serial-link systems like USB 3.0 or PCI Express Generation II. Therefore, an equalizer which can operate in bursted data becomes more and more important. An activity detector is used to play the role to detect whether the data is bursting or not. A digitally adaptive controller is used to memorize the adaptation information when data is under the idle state. By using digitally adaptive controller and activity detector, the reaction time of burst-mode communication can achieve only 5.5ns or 33bit-time. Furthermore, the conventional interpolation weighting control scheme suffers from delay mismatch between the all-pass path and the peaking path. The strong overshoot in the peaking path also suffers from non-linearity problem under short channel applications. Therefore, a pipelined equalizing filter is proposed for the application in high channel loss with wide tuning range. By switching off the unused stages, the proposed pipelined equalizing filter can also achieve better power efficiency. Fabricated in 0.18μm CMOS technology, the equalizer is capable of running at 6Gb/s over a 90-inch FR4 printed-circuit-board while consuming 26.7mW from a 1.8V supply.