高陣列面積效率之次臨界電壓靜態隨機存取記憶體和資料感知保持器

Abstract

靜態隨機存取記憶體在系統晶片中扮演著很重要的角色，由於先進製程之變異量比以往嚴重，而且在低電壓下的Ion/Ioff比率較低，傳統6T和8T靜態隨機存取記憶體在低電壓下無法正確操作。 在此論文，首先提出一個具備資料感知電源切斷寫入輔助技術之字串分離次臨界電壓11T靜態隨機存取記憶體。此資料感知電源切斷寫入輔助技術可用於改善因為製程變異和自串分離架構所帶來的寫入失敗問題.在一個40奈米製程所生產之4Kb測試晶片中，最低操作電壓被讀取操作限制在0.32伏特。(約為0.69倍的臨界電壓) 而寫入的最低操作電壓為0.31伏特。 再來提出一個新的資料感知電源切斷寫入輔助技術之12T記憶胞，藉此解決上述11T記憶胞在寫入過程中行半選的記憶胞的資料流失問題。由於緊密且對稱的布局技巧，這個12T記憶胞面積可以比上述的11T記憶胞小百分之四。在20000次的蒙地卡羅模擬中，此12T記憶胞的的資料保存和寫入能力階非常可靠，在0.25伏特操作電壓下發生寫入錯誤之機率僅為0.025%。採用12T記憶胞解決了寫入問題後，再提出具有漏電感知能力之保持器(Keeper)來解決因為未選記憶胞之漏電累積所造成之讀取問題。透過40奈米CMOS製程，上述之12T記憶胞與漏電感知保持器被實現成8Kb(64*128)之靜態隨機存取記憶體。在隨機變異模擬中，這個8Kb 12T靜態隨機存取記憶體可正確地以3.3MHz之速度工作在0.28伏特的低電壓下，此電壓乃是受限於讀取操作。由於長位元線的架構能夠減少周邊電路之面積，所以在這個8Kb 12T靜態隨機存取記憶體中，總面積為14614平方微米，平均每個位元之面積僅為1.785平方微米。

Static Random Access Memory (SRAM) plays an important role in the System on Chip (SOC) design. Because of the large process variation in the advanced process and the small Ion/Ioff ratio at low voltage, the traditional 6T and 8T SRAM can’t work when operating at low voltage. In the thesis, first, a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware-Power-Cutoff (DAPC) Write-assist is proposed to mitigate the Write-ability problem caused by the process variation and bit-interleaving structure. Measurement results of a 4Kb test chip implemented in 40nm General Purpose (40GP) CMOS technology shows that VDD can down to 0.32V (~0.69X of threshold voltage) with operation speed of 3.5MHz with VMIN limited by Read operation. And the Write VMIN is 0.31V. Second, a new Data-Aware-Power-Cutoff 12T SRAM cell is proposed to solve the column-half-select-data-retention problem which happens during Write operation in the previous 11T SRAM cells. Because of the compact and symmetric layout style, the cell area of this 12T cell is smaller than previous 11T cell by 4%. According to the 20000 times Monte-Carlo simulation in 40GP, the Hold ability and Write ability of this 12T cell are very reliable. The error rate is 0.025% with the VDD down to 0.25V. After solving the Write problem by the 12T cell, a Pattern-Aware-Keeper is proposed to solve the Read problem caused by the accumulation of leakage of unselected cells in the long bit line condition. The Pattern-Aware-Keeper and 12T cell are implemented as a 8Kb (64X128) SRAM in 40nm General Purpose (40GP) CMOS technology. In the simulation with random local variation, this 8Kb 12T SRAM is fully functional at 0.28V with the operation speed of 3.3MHz, and the VMIN is limited by Read operation. Because the long bit line structure can reduce the area of peripheral circuit, the total area is 14614 um2 (253.535um □ 57.64um) and the area per bit is just 1.785 um2 in this 8Kb 12T SRAM.