完整後設資料紀錄
DC 欄位語言
dc.contributor.author陳明志en_US
dc.contributor.author陳正en_US
dc.date.accessioned2014-12-12T01:58:15Z-
dc.date.available2014-12-12T01:58:15Z-
dc.date.issued2003en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009117566en_US
dc.identifier.urihttp://hdl.handle.net/11536/50046-
dc.description.abstract隨著個人攜帶式應用產品的普及,對於影音資料與即時性資料的需求日益增加,因此,數位訊號處理器扮演的角色也日趨重要。如何能使資料即時且正確的展現在使用者面前成了一個重要的課題,而指令的排程在整個過程中是一個很關鍵的步驟。我們利用Retiming的觀念,設計了一個在有限資源情況下的排程方法,名為Bottom Retiming Scheduling Method,改善了Relax Push-Up Scheduling Method會造成較大maximum retiming depth的缺點。另外,由於可攜帶式的產品大都由電池供電,如何降低消耗功率以延長使用時間,亦是一個重要的課題;我們以Bottom Retiming Scheduling Method為基礎,加入了operand sharing可以減少switching activities的觀念,設計了一個降低功率消耗的指令排程方法Bottom Retiming with Operand Sharing Method。由實驗結果可以看出,這兩個方法都可以達到不錯的效果。zh_TW
dc.description.abstractBecause portable devices become popular, digital signal processing on images and real-time data are more and more important. How to process data correctly in real-time is one of the most interesting topics to be investigated. The instruction scheduling is an important step through the whole process. Under resources constraints, we use retiming technique to design a method named Bottom Retiming Scheduling Method. It overcomes the shortcoming of Relax Push-Up Scheduling Method which is a bigger maximum retiming depth. Besides data throughout, low power consumption is another important issue for portable devices. Based on Bottom Retiming Scheduling Method, we integrate the operand sharing technique which can reduce switching activities to design another method named Bottom Retiming with Operand Sharing Method for low power scheduling. The experimental results show the effectiveness of these methods.en_US
dc.language.isoen_USen_US
dc.subject巢狀迴圈zh_TW
dc.subject指令排程zh_TW
dc.subject功率消耗zh_TW
dc.subjectnested loopen_US
dc.subjectschedulingen_US
dc.subjectlow power consumptionen_US
dc.subjectretimingen_US
dc.title針對數位訊號處理器中的巢狀迴圈考慮功率消耗的指令排程方法zh_TW
dc.titleInstruction Scheduling with Less Power Consumption for Nested Loop on DSP Architectureen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
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