嵌入式系統異質雙核心Java處理器設計

Abstract

本論文為Java處理器提出了一個異常處理的設計。雖然目前有許多關於Java處理器設計的相關研究，但是大部分的研究簡單地忽略了異常處理，而有些聲稱，符合Java語言的異常處理機制牽涉到複雜的行為而難以實作在硬體上。在這篇論文中，我們檢視了異質雙核心Java處理器對於例外處理的機制有優秀的硬體加速效果，進而提出了一個以硬體設計為主的異常處理機制，除此之外，為了能夠支援有效率的例外處理機制，我們還改善了此平台上二層級方法區域的設計，在實作出來的例外處理機制設計中，並不會影響正常程式的執行效能，而只有當程式真正發生異常時，才會增加異常處理的時間，更重要的是，由於異常處理的程序主要執行於Java核心，因此大大節省了處理器之間的溝通時間，我們實作上述完整的Java執行環境在Xilinx ML-507 FPGA開發板上，在最後的實驗數據結果顯示，我們提出的硬體異常處理機制非常適合用在Java嵌入式平台的環境並且有非常好的效能。

This thesis presents the design of the exception handling architecture of a Java processor. Although there are many research publications on Java processor designs, there is no efficient implementation on Java exception handling circuitry. Most Java processor design papers simply ignore exception handling while some claims that a hardwired implementation of exception handling conforming to the Java language specification is quite complex to implement. In this thesis, we have proposed an efficient design of the Java exception handling mechanism and the associated two-level method area. We have also integrated the design into a heterogeneous dual-core Java processor. With the proposed two-level method area, the exception handling overheads are delayed to the time after an exception actually occurs. More importantly, the process of exception handling is mostly performed in the Java core with very little runtime overhead from the RISC core. As a result, the proposed design reduces the amount of inter-processor communication and circuit design cost of the Java core while enabling full support of Java exception handling. We have implemented the design on a Xilinx ML-507 FPGA platform. As the experiments show, the proposed design is very promising for embedded applications.