| 标题: | EASILY TESTABLE SEQUENTIAL-MACHINES WITH EXTRA INPUTS AND EXTRA OUTPUTS |
| 作者: | DAS, SR CHEN, Z DAI, YL 交大名义发表 资讯工程学系 National Chiao Tung University Department of Computer Science |
| 公开日期: | 1980 |
| URI: | http://hdl.handle.net/11536/5060 |
| ISSN: | 0013-5194 |
| 期刊: | ELECTRONICS LETTERS |
| Volume: | 16 |
| Issue: | 4 |
| 起始页: | 119 |
| 结束页: | 121 |
| 显示于类别： | Articles |
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- RESTRUCTURING AND LOGIC MINIMIZATION FOR TESTABLE PLA / HWANG, GH;SHEN, WZ
- SIMPLIFYING SEQUENTIAL-CIRCUIT TEST-GENERATION / SHEU, ML;LEE, CL
- 应用于硬体描述语言的一个有效率设计验证辅助技术 / 陈怡伶;I-Ling Chen;周景扬;Jing-Yang Jou
- A design-for-verification technique for functional pattern reduction / Liu, CNJ;Chen, IL;Jou, JY
- FAULT-DETECTION IN SEQUENTIAL-MACHINES WITH INCREASED FAULT COVERAGE / DAS, SR;BHATTACHARYYA, A
- A design-for-digital-testability circuit structure for Sigma-Delta modulators / Hong, Hao-Chiao
- Finite state machine synthesis for at-speed oscillation testability / Li, KSM;Lee, CL;Jiang, T;Su, CC;Chen, JE
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