完整後設資料紀錄
DC 欄位語言
dc.contributor.author黃賢生en_US
dc.contributor.authorHsien-Sheng Huangen_US
dc.contributor.author謝太炯en_US
dc.contributor.authorTai-Chiung Hsiehen_US
dc.date.accessioned2014-12-12T02:02:57Z-
dc.date.available2014-12-12T02:02:57Z-
dc.date.issued2003en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009121519en_US
dc.identifier.urihttp://hdl.handle.net/11536/51957-
dc.description.abstract本論文研究一個符合IEEE802.11b的互補式金氧半頻率合成器之設計。電路主要透過國家晶片系統中心,以台灣積體電路製造股份有限公司提供的0.25μm製程技術來實現。我們所設計的頻率合成器為雙電荷沯浦的架構,包含四相位輸出之壓控振盪器、除頻器、相位頻率偵測器、電荷沯浦及低通濾波器,操作電壓為2.5V。所設計的頻率合成器經由ADS模擬,顯示電路可以正常工作,其中壓控振盪器除了模擬外,晶片也製作量測完成。 模擬結果顯示,所設計的頻率合成器在2.5V的工作電壓下,參考訊號為10MHz,輸出頻率為2.4GHz到2.526GHz,每10MHz一個間隔,共為64個頻率,輸出功率大小-6dBm,共消耗功率約53.76mW。壓控振盪器的模擬結果輸出頻率從2.25GHz到2.68GHz,增益約為-450MHz/V,輸出功率最大可到-5.29dBm,四個輸出彼此間隔90∘,而總消耗功率為48.41mW。其相位雜訊在100kHz時為-98.28dBc/Hz。壓控振盪器的晶片量測數據主要有:消耗功率為39.5mW,輸出頻率範圍從2.097GHz到2.315GHz,增益為-167MHz/V,最大的輸出功率為-9.3dBm,相位雜訊在100KHz時為-75.47dBc/Hz,相位誤差為10.2∘。zh_TW
dc.description.abstractIn this thesis, a CMOS frequency synthesizer is studied and designed to meet the IEEE802.11b standard. This frequency synthesizer has a two-charge-pump structure. It includes a quadrature voltage-controlled oscillator (VCO), frequency divider, phase frequency detector, charge pump and low-pass filter, and operates at 2.5-V power supply. The synthesizer circuit is simulated by ADS. The simulation results show that this circuit can fulfill the design specifications. Besides the simulation study, VCO is fabricated by TSMC 0.25μm process. The designed frequency synthesizer can be operated well with 10-MHz reference frequency at 2.5-V power supply. ADS-simulation shows that this synthesizer deliver output frequency from 2.4 GHz to 2.526 GHz with a spacing 10 MHz. Its output power is -6 dBm and the total power consumption is 53.76 mW. The quadrature VCO’s simulation results reveal that the output frequencies are tunable from 2.25 GHz to 2.68 GHz, and VCO’s gain is about -450 MHz/V. Its maximum output power is -5.29dBm, the phase difference of the four output is 90∘, and the total power consumption is about 48.41 mW. The phase noise is -98.28 dBc/Hz at 100-kHz offset frequency. In the real chip implementation,the VCO has been measured with the output frequencies tunable from 2.097 GHz to 2.315 GHz. The VCO’s gain is -167 MHz/V, and has total power consumption 39.5 mW. The maximum output power is -9.3dBm, the phase noise is -75.47 dBc/Hz at 100-kHz offset frequency and the phase difference of the VCO outputs is deviated from 90∘by a magnitude of 10.2∘.en_US
dc.language.isozh_TWen_US
dc.subject頻率合成器zh_TW
dc.subject壓控振盪器zh_TW
dc.subject四相位zh_TW
dc.subject雙電荷沯浦zh_TW
dc.subject除頻器zh_TW
dc.subjectfrequency synthesizeren_US
dc.subjectVCOen_US
dc.subjectquadratureen_US
dc.subjecttwo charge pumpen_US
dc.subjectfrequency divideren_US
dc.title符合於IEEE802.11b互補式金氧半頻率合成器設計zh_TW
dc.titleThe Design of CMOS Frequency Synthesizer for IEEE802.11ben_US
dc.typeThesisen_US
dc.contributor.department電子物理系所zh_TW
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