标题: | 分离式闸极非挥发性记忆体技术及新颖多晶矽电子抹除式唯读记忆体之研究 Study on Split-Gate Non-Volatile Memory Technology and A Novel Single Poly EEPROM Memory Cell |
作者: | 宋弘政 Hung-Cheng Sung 雷添 福 Tien-Fu Lei 电子研究所 |
关键字: | 分离式闸极;非挥发性记忆体;电子抹除式唯读记忆体;split-gate;Non-Volatile Memory;EEPROM |
公开日期: | 2007 |
摘要: | 在此论文,首先,我们发展了一种新的方法来作分离式闸极快闪记忆体的写入及干扰空间的量测。这个方法能帮助我们定量地了解操作空间的变化与电压的关系,进而,这方法可以用来找到最佳化的写入条件。由此方法找到的条件可以承受最大的电压变化。我们成功地运用这方法在新一代的分离式闸极快闪记忆体的发展。 再者,一种新颖的三重自动对准分离式闸极快闪记忆元在此论文被揭露。此记忆元有T型的耦合结构,此新结构能大幅地增加源极和浮动闸极间的耦合电容而不需要记忆元面积的增加,此改善是藉由一个氧化层蚀刻的步骤来调变。此结构能用于写入电压的降低及记忆元的缩小。对于写入电压的降低,最高电压可由7.4V降至6.4V。而对于记忆元的缩小,我们成功地降低浮动闸极的长度由0.18µm到0.14µm而没造成良率的下降或者可靠度的衰退。 最后,一种有着金属控制闸极的新颖单多晶矽电子抹除式唯读记忆体EEPROM在此论文中被发表。它的金属闸极是由嵌刻(damascene)制程作成的钨(W)线,它的闸极间的介电层是由原子磊晶长成的氧化铝(Al2O3)。它的写入/抹除的操作方式和传统的堆叠闸极(stack-gate)记忆元是相同的,它用通道热电子注入做写入及用FN穿隧做抹除。因氧化铝有着高介电常数的特性,所以我们可以用小于6.5V的电压来执行写入及抹除,而此电压可以用3.3V的元件来操作,而不用使用到传统的高压元件。在制程相容方面,此记忆体只需比传统CMOS制程多出二道光罩既可,此外,这氧化铝是在后段制程中完成,所以此技术没有污染的顾虑以及额外高温制程所造成的元件影响。因此,此技术非常能适用于嵌入式产品的应用。在此论文中,我们发表了良好的记忆体特性,如快速的写入及抹除还有良好的重覆写入/抹除特性及资料持久性。 In this thesis, first, we developed a new methodology for program vs disturb window characterization on split gate flash. This method can help us to understand quantitatively how the window shifts vs bias conditions; furthermore, find the optimal program condition. The condition obtained by this method can withstand the largest program bias variations. This methodology was successfully implemented in the development for new generation of split-gate cell Secondly, a new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling structure is described in this paper. This novel structure can significantly enhance coupling capacitance between the source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6.4 V. For cell size scaling, we successfully reduce the floating length from 0.18µm to 0.14µm without showing the yield loss or reliability degradation. Finally, a novel single poly EEPROM with metal control gate structure is presented in this paper. The control gate is tungsten (W) line made by a damascene process, and inter-gate dielectric is Al2O3 grown by Atomic Layer Deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim (F-N) tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-K material is deposited in the back-end metallization steps, so there is no cross-contamination issue caused by new material nor the device impact induced by the extra thermal cycle from conventional double poly process. Therefore, this new technology is suitable for embedded application. In this paper, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance cycling and data retention. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT008811806 http://hdl.handle.net/11536/53446 |
显示于类别: | Thesis |
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