高速乘法器設計及其自動布局產生器

Abstract

本篇論文介紹了一種新的，適合於超大型積體電路製作的高速並行乘法器 設計方法。同時它也具備了自動產生布局的能力。我們設計了一個新的架 構及兩個加法器，使得所設計出的乘法器除了具備高速運算的能力外，在 電路上並力求規則化及模組化。如此不但可以簡化設計的複雜度，同樣的 方法還可以很容易地擴充到任何位元長度的乘法器製作上。此外，為了能 達到自動產生布局的目的，在設計上我們盡量設法簡少電路上的複雜度， 使其重複性提高。最後，我們利用互補式金氧半Ｎ井區０．８微米的技術 實際設計及製作了一個二補數之乘法器的自動布局產生器。其延遲時間可 由SPICE模擬得知。由於乘法器的位元長度未定，詳細結果將列於本文中 。其數量值為１０奈秒左右。 A new design methodology of high speed multiplier suitable for VLSI implementation is proposed. The new multiplier is characterized as the one that acheves a highly regular and modularized circuitry. Some new adder cells are employed to reach the high speed criterion. In addition, a new architecture is proposed for automatic layout generation. In this architecture, simple and modular cells are used to construct the multiplier which enable an easier and less error-prone design. Further more, the designed architecture can be easily extended to any word length and the data control signals are very simple. In order to cope the large loading resulting from sign extension, a method is proposed with little hadrware cost. Because we have to generate the multiplier layout automatically, a tradeoff on the multiplier's area-time complexity is also taken into consideration carefully such that a high speed operation is obtained only on a suitable circuit complexity. Finally, the two's complement multiplier is design and implemented using TSMC 0.8um single poly double metal process, and it is easily extended to any word length. The delay time of the multiplier is various from defferent word length. The detail is shown in the thesis.