非晶矽薄膜電晶體的計測與分析

Abstract

本論文提出有關金屬╱絕緣層╱非晶矽結構及薄膜電晶體元件之電容－電 壓和電流－電壓模型，以萃取非晶矽膜能隙中的能態分佈以及等 效載子 移動率對閘極電壓的對應關係。此外，從通道長度較短之薄膜電晶體元件 的實驗電流－電壓特性，源╱汲極寄生電阻及通道長度偏差可以藉由所發 展的電流－電壓模型萃取出參數萃取的程序及其方法也加以討論。仿照金 氧半結構可靠度的研究方法，我們研究氮化物╱非晶矽金絕半結構及薄膜 電晶體元件在不同應力條件下的電容－電壓及電流－電壓特性，並對載子 捕獲機制加以討論。當電荷陷於氮化物的機制為主時，電壓的偏移量可以 表示成應力時間的次冪函數。 This thesis presents the analytic C-V and I-V models for MIS (a-Si) structure and the TFT device to extract the gap-st- ates distribution in the a-Si film and the gate-voltage depen- dence of the effective carrier mobility. In addition, the sou- rce/ drain parasitic resistance and the channel-length deviation can be extracted by the developed I-V model from the experime- ntal I-V characteristics of shorter TFT devices. The extraction procedure and its methodology are discussed. Following the example of MOS reliability researches, the C -V and I-V characteristics of the nitride/a-Si MIS structure and TFT devices under different stress conditions are investi- gated and their trapping mechanisms are discussed. It is shown that when the charge trapping in nitride dominates, the voltage shift can be simply expressed as a power function of stress time.