新型電擦拭可程式化僅讀記憶器元件之分析及設計

Abstract

在本論文中，我們提出並分析一個利用P-通道複晶矽之薄膜電晶體 (TFT) 來輔助抹除的新型電擦拭可程式化僅讀記憶器(EEPROM)元件.此薄膜電晶 體是被做在傳統疊閘(Stacked-Gate)架構之快閃式擦拭可程式化僅讀記憶 器(Flash EEPROM)元件的第二複晶矽層上.在此新元件中,是利用由薄膜電 晶體產生的熱電洞注入懸浮閘(Floating-Gate)來完成元件的抹除動作.因 為在短通道P型薄膜電晶體中,熱電動效應會比在單晶電晶體中還嚴重.所 以較有效率的抹除動作是可預期的.除此之外,由於不同的寫入/抹除路徑, 亦可減低氧化層崩潰(Oxide Braekdown)效應的發生進而增加元件的可靠 性.此新元件不僅為電擦拭可程式化僅讀記憶器元件,亦可做為快閃式電擦 拭可程式化僅讀記憶器元件.由TMA MEDICI模擬器的模擬結果可證明元件 的抹除動作.其顯示出與傳統的電擦拭可程式化僅讀記憶器比較,在相近的 工作電壓下,此新元件的抹除時間可縮短至數十微秒.電擦拭可程式化僅讀 記憶器元件的最佳化設計,及其實驗驗證,將為吾人未來研究的方向. In this thesis, a new EEPROM cell using the p-channel poly- Si TFT for erasure operation is proposed and analyzed. The TFT device is fabricated on the seond poly-silicon layer of conven- tional stacked-gate flash EEPROM. In the proposed new EEPROM device, the hot-hole injection from the TFT device to the float- ing gate is used for cell erasure. Since the hot-hole generation in the short channel p-channel TFT devices is more serious than that in the single-crystalline MOSFETs, an effective erasure is expected. In addition, the different program/erase paths in our device can reduce the occurrence of oxide breakdown and increase the reliability. The proposed cell can be used as the normal EEPROM cell and the flash EEPROM cell. From the simulation re- sults using the TMA MEDICI simulator, the erase operation has been verified. It is shown thatthe erase time can be reduced to tens of microseconds with the comparable erasing voltages as in the conventional EEPROM. Future researches on device optimiza- tion, experimental verification, and real EEPROM design will be done.