标题: | 新型电擦拭可程式化仅读记忆器元件之分析及设计 Analysis and Design of a New EEPROM Device |
作者: | 杨正一 Cheng-Yi Yang 吴重雨 Chung-Yu Wu 电子研究所 |
关键字: | 写入;抹除;悬浮闸;氧化层崩溃.;Program;Erase;Floating gate;Oxide breakdown. |
公开日期: | 1993 |
摘要: | 在本论文中,我们提出并分析一个利用P-通道复晶矽之薄膜电晶体 (TFT) 来辅助抹除的新型电擦拭可程式化仅读记忆器(EEPROM)元件.此薄膜电晶 体是被做在传统叠闸(Stacked-Gate)架构之快闪式擦拭可程式化仅读记忆 器(Flash EEPROM)元件的第二复晶矽层上.在此新元件中,是利用由薄膜电 晶体产生的热电洞注入悬浮闸(Floating-Gate)来完成元件的抹除动作.因 为在短通道P型薄膜电晶体中,热电动效应会比在单晶电晶体中还严重.所 以较有效率的抹除动作是可预期的.除此之外,由于不同的写入/抹除路径, 亦可减低氧化层崩溃(Oxide Braekdown)效应的发生进而增加元件的可靠 性.此新元件不仅为电擦拭可程式化仅读记忆器元件,亦可做为快闪式电擦 拭可程式化仅读记忆器元件.由TMA MEDICI模拟器的模拟结果可证明元件 的抹除动作.其显示出与传统的电擦拭可程式化仅读记忆器比较,在相近的 工作电压下,此新元件的抹除时间可缩短至数十微秒.电擦拭可程式化仅读 记忆器元件的最佳化设计,及其实验验证,将为吾人未来研究的方向. In this thesis, a new EEPROM cell using the p-channel poly- Si TFT for erasure operation is proposed and analyzed. The TFT device is fabricated on the seond poly-silicon layer of conven- tional stacked-gate flash EEPROM. In the proposed new EEPROM device, the hot-hole injection from the TFT device to the float- ing gate is used for cell erasure. Since the hot-hole generation in the short channel p-channel TFT devices is more serious than that in the single-crystalline MOSFETs, an effective erasure is expected. In addition, the different program/erase paths in our device can reduce the occurrence of oxide breakdown and increase the reliability. The proposed cell can be used as the normal EEPROM cell and the flash EEPROM cell. From the simulation re- sults using the TMA MEDICI simulator, the erase operation has been verified. It is shown thatthe erase time can be reduced to tens of microseconds with the comparable erasing voltages as in the conventional EEPROM. Future researches on device optimiza- tion, experimental verification, and real EEPROM design will be done. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT820430040 http://hdl.handle.net/11536/58039 |
显示于类别: | Thesis |