CMOS 低功率數值控制振盪器之晶片設計

Abstract

在本論文中，我們設計一低功率之數值控制振盪器晶片。其功能特徵包 括: 48位元之頻率解析、12位元之振幅解析及15位元之相位解析、正弦或 餘弦之二補數或二進位偏移輸出碼、微處理器匯流排之控制輸入、和具 3.3伏特或5伏特可供選擇之電源。為達到低功率之要求，我們採用管狀架 構的累加器和一些ROM 的壓縮技巧; 此外，也設計了位於晶片內的降壓轉 換器和供正弦或餘弦查表用的低功率單相位PLA。此一晶片採用 0.8 um SPDM 的CMOS生產技術，佔用10.6mm^2 的面積，內含二萬三千顆電晶體。 模擬結果，此振盪器能操作在50MHz的頻率，平均消耗功率約130mW。 A low-power numerically controlled oscillator (NCO) chip is presented in this paper. The features of this chip include 48-bit frequency resolution, 12-bit amplitude resolution and 15-bit phase resolution, 2's complement or offset binary and an alter- native power supply of 3.3V of 5V. TO achieve low power, a pipe- lined accumulator structure and several ROM compression methods are used. In addition, an on-chip voltage down converter and a low-power single phase PLA for sine/cosine lookup table were implemented. This chip consists of 23,000 transistors in an area of 10.6 mm^2 using 0.8um SPDM CMOS techology. The simulation results indicate that it can run at a clock rate of 50MHz and an average power consumption of 130mW.