互補式金氧半暫態鎖住效應及晶片上靜電放電保護電路之研究.

Abstract

本論文可分成兩部份，一是對互補式金氧半(CMOS)中的鎖住效應加以 深入探討，另一是有關互補式金氧半積體電路的靜電防護技術之研究。藉 由對鎖住效應的深入了解與研究，本論文利用互補式金氧半中寄生的矽控 整流器(SCR)特性，設計出新型的靜電防護電路。本論文把原本在積體電 路中是缺點的鎖住效應變做成靜電防護技術中的優點。 本論文對動態 ╱暫態鎖住效應做深入的探討，提出一個判斷鎖住效應發生的準則，此準 則包含元件電容上的暫態電流在內。進一步推導此一準則的明顯數學式， 本論文利用區段線性化的技巧推導出一個暫態鎖住效應的時序模式。利用 此時序模式，各種激發源來激發鎖住效應所需時間皆可利用此時序模式計 算出來。另外，為模擬動態鎖住效應中的正迴授現象，本論文提出一個大 信號暫態正極點模式。利用此正極點模式，鎖住效應中的正迴授機制可以 被定量地計算。 本著對互補式金氧半中鎖住效應的充分了解，本論文 利用互補式金氧半中寄生的矽控整流器來做靜電放電保護電路。已設計出 暫態觸發矽控整流器型靜電防護電路，測試結果顯示有極佳的效用。在本 論文中，共提出三種保護電路之架構，第一種是用雙矽控流器結構；第二 種是用互補式矽控整流器結構；第三種是用四個矽控整流器結構。這些矽 控整流器型靜電防護電路皆能夠在小的佈局面積內，提供高的靜電防護能 力，故可達到高密度的應用。 This dissertation includes two parts. The first part is the physical analysis of the CMOS transient latchup in the parasitic p-n-p-n path of CMOS ICs. The second part is the application of SCR devices on the ElectroStatic Discharge (ESD) protection circuits. A new physical criterion and an analytical timing model for trnasient latchup in a p-n-p-n structure are developed and verified. With the piecewise-linearized method, a timing model of transient latchup in terms of device parameters is derived. Model calculation results using the developed criterion and timing model agree very well with both SPICE simulation and experimental results. In order to deeply characterize the mechanisms of the positive-feedback regeneration during CMOS latchup transition, a novel method is developed. The positive-feedback regeneration in a p-n-p-n structure can be definitely modeled by this positive transient pole method. Based on the clear understanding on the transient latchup mechansim in the p-n-p-n structure of CMOS ICs, there are three robust CMOS on-chip ESD protection circuits with the lateral SCR devices proposed in this thesis. The first is the dual-SCR ESD protection circuit which consists of dual parasitic SCR structures between input and VDD node. The second is the complementary-SCR ESD protection circuit which consists of two parasitic lateral SCR devices and two junction diodes merged together to save more layout area. The third is the four- SCR ESD protection circuit which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities to either VDD or VSS(GND) nodes.