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dc.contributor.author黃國豪en_US
dc.contributor.authorHuang, Guo Haoen_US
dc.contributor.author沈文仁en_US
dc.contributor.authorShen, Wen Renen_US
dc.date.accessioned2014-12-12T02:12:48Z-
dc.date.available2014-12-12T02:12:48Z-
dc.date.issued1993en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT822430003en_US
dc.identifier.urihttp://hdl.handle.net/11536/58515-
dc.language.isoen_USen_US
dc.title可程式邏輯陣列之合成與測試zh_TW
dc.titleSynthesis and testing of programmable logic arraysen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis