全晶圓積體電子式固態硬碟佈局設計

Abstract

全晶圓積體(Wafer Scale Integration)是在使用整個晶圓去設計一個電 路系統的方法。WSI相對於一般VLSI有下列優點：低耗電、小體積、高速 度（較短的內部接線）及較低的整體花費。但由於佈局面積的擴大使一些 問題變得非常重要；例如功率的消耗及時脈的同步問題，在全晶圓積體的 設計上已成為整個系統效能的關鍵問題。另一個重要的問題是容錯能力的 考慮，如何去避開有缺陷的單元且有較高的收穫率(harvest rate)也是全 晶圓積體可行與否的因素。全晶圓的固態硬碟的製作是在一晶圓上佈滿相 同的記憶體模組，並以容錯連結連接之，因此我們可以避開在生產過程中 產生的瑕疵電路而不會影響整個系統的動作。在本論文中，我們將描述全 晶圓積體電子式固態硬碟的佈局。電子式硬碟是由晶圓上的相同記憶體模 組組成。記憶體模組是採用迴圈式容錯連結方式連接，它提供簡單的重組 程序而且能有高的收穫率。模組中也提供了內建的測試指令，所以系統的 測試能以管道的方式進行，以減低整體的測試時間。我們也利用國科會 CIC提供的支援製作了一顆包含四個模組的電子式硬碟實驗原型晶片。我 們採用SPICE程式來模擬三種電源佈局方式，五種時脈佈局方式。我們假 設每個模組的容量為16Mb，模組的佈局面積為48mm2，功率消耗為33mA。 一個五吋的晶圓上共包含196個模組。模擬的結果顯示電源和地線的寬度 至少要500μm，才能提供穩定的電源供應。在五種時脈佈局方式中，寬主 幹線-連結次緩衝器的方式有最好的效能；它的最大相位差為2.80ns，昇/ 降緣時間為2.98ns/ 2.62ns。我們也描述了全晶圓積體電子式固態硬碟的 佈局。在一個單一晶圓上，電子式硬碟的容量為392MB，資料傳輸頻寬大 約為6MB /sec。 Wafer Scale Integration(WSI) uses an entire wafer to implement a digital system. WSI offers many advantages such as lower power consumption, small volume, high speed , and low system costs. However due to large layout area of a wafer, some design issues critical, such as power distribution, and clock synchronization. Another important design issue of WSI design is defect-tolerant abilities. How to bypass defect modules and to harvest as many good module as possible is the key problem for WSI design. In this thesis, the layout design of a WSI Solid- State Disks(SSD) is described. The SSD consisted of identical memory modules on a wafer. The memory modules are interconnected by a loop-based defect-tolerant linear array interconnection. Which offers simple reconfiguration procedure and yet high harvest rate. Verification commands are also implemented in the module so that system testing can be done in a pipelining fashion to reduce the overall testing time. A prototype IC which consists of four modules is fabricated under the support of CIC, NSC. Spice simulations are also used to evaluate three schemes of power distribution. and five schemes of clock distribution. We assume that each module has the capacity of 16Mb, the area of 48mm2, and the current dissipation of 33mA. A 5-inch wafer can contains 196 modules. The simulation results show that the width of the power and ground line must at least 500um to support a stable power supply. Among the five schemes of clock distribution, wide- trunk with separate sub-buffers approach offers the best performance; the clock skew is less than 2.8ns, the rising/ falling time is 2.98ns/2.62ns. The layout design of the WSI SSD is also described. As a single wafer, the SSD design provides 392 MB capacity, and its data transfer bandwidth is estimated at 6 MB/sec.