寬頻整合服務數位網路之可容錯非同步傳輸模式交換鍵設計及實現

Abstract

在本篇論文中，我們提出一種新的方法來建構可容錯非同步傳輸模式交換 鍵。藉著這種方法，任一輸入輸出對都具有兩條不相互重疊的路徑。此交 換鍵的主要元件為一個具有兩個輸入端與兩個輸出端的容錯交換單元，它 可以做為高速非同步傳輸模式交換鍵的基本建構單元。基於容錯交換單元 的可容錯非同步傳輸模式交換鍵是根據多種選擇路徑及自我搜尋路徑的原 則下來設計。這個容錯交換單元藉著加入少許的備用元件如一個備用的輸 入控制器與兩個備用的輸出控制器到傳統的交換單元來達到容錯的能力。 藉由數學分析我們得到的結論是此非同步傳輸模式交換鍵比其它的交換鍵 使用較少的交換單元及有較多的多餘路徑。為了消除阻隔的問題，我們在 容錯交換單元中採用了兩個共用的緩衝器。採用共用的緩衝器不但使得緩 衝器的使用更具有彈性而且使其具有容錯的能力。我們以標準硬體描述語 言來描述這個非同步傳輸模式交換鍵。由標準硬體描述語言的模擬，我們 驗證了此非同步傳輸模式交換鍵功能的正確性。我們也藉著合成方式實現 此非同步傳輸模式交換鍵，以計算其延遲時間與面積大小。模擬與合成的 結果證明我們所提出的基於容錯交換單元的可容錯非同步傳輸模式交換鍵 比其它的交換鍵提供了更佳的可靠度與硬體成本比率。 In this thesis, we propose a new method to build a fault tolerant ATM switch. By this method, we can build an ATM switch which has two non-overlapping paths between each input/output pair. The key component in the proposed switch is a 2x2 FTSE (Fault Tolerant Switching Element) which can be the basic building block for high speed ATM switches. The design of the FTSE-based fault tolerant ATM switch is based on a multi-path, self-routing principle. The FTSE is made with the ability of fault tolerance by adding a few spares to the traditional Switching Element (SE) : mainly one spare Input Controller (IC) and two spare Output Controllers (OCs). By mathematical analysis, we conclude that our ATM switch uses less SEs and have more redundant paths than the other ATM siwtches. To eliminate the blocking problem we provide two shared buffers in the FTSE. The two shared buffers can make the usage of the buffers more efficient and fault tolerant as well. The ATM switch has been described by using VHDL. By VHDL simulation, we have verified the functionality of the switch. We also synthesize the ATM switch to evaluate its delay and area. The simulation and synthesis results demonstrate that the reliability/cost ratio of the FTSE-based fault tolerant ATM switch is better than that of other switches.