應用於IS-54的VITERBI解碼器設計

Abstract

在二十一世紀初，無線電話將大量增加，約有一半的人口需此服務。可是 現有之類比系統，無法滿足此服務需求，因此在歐洲、北美和日本相繼推 出分時多工存取 (TDMA) 細胞狀的無線電話標準，以增加通道的容量，使 符合達到個人通訊 (personal communication) 所要的大部份改善。在北 美的分時多工存取 (TDMA) 細胞狀的無線電話標準─ IS-54, 將每個使用 者每秒可傳輸的 16,200 bits 的資料量分成語音─每秒 7,950 bits、 語音保護碼─每秒 5,050 bits、SACCH ─每秒 600 bits 和其它同步等 ─每秒 2,600 bits。本篇論文提出一 Viterbi 解碼器電路，此電路具有 軟式決定 (Soft Decision) 解碼、 ACS 分享 (sharing) 和 systolic 存活記憶體管理 (survivor memory management)。存活記憶體 管理的控制相當簡單，且其繞線 (wiring) 相當規則， 不像 register exchange 演算法那般的複雜。此電路的解碼速率可達到每秒 12.5 百萬 bits，可符合 IS-54 中語音保護碼解碼的速率要求。當考量到速度和面 積，此解碼速率可更快，只需改變加法器和減法器的電路， 而毋需改變 整個電路架構。 此晶片大小 (core size) 為 3.3(mm)x3.6(mm)。 The market for cellular radio telephony is expected to increase dramatically during the 2000's. Service may be needed for 50% of the population. This is beyond what can be achieved with the present generation analog cellular systems. The evolving digital time division multiple access (TDMA) cellular standards in Europe, North America, and Japan will give important capacity improvements and may satisfy much of the improvement needed for personal communication. In this thesis, a Viterbi decoder was proposed. The circuit features soft decision decoding, ACS sharing, and systolic survivor memory management. The control signal of systolic memory management is very simple and the wiring is quite regular, not like register exchange algorithm. Its maximum decoding rate can reach 12.5 MHz, so it is suitable to IS-54 for error protection of speech. The speed can be further increased by modifying the datapath of adder and comparator basing on the requirement area or speed. The modification does not need to alter the architecture. The core size of the Viterbi decoder is 3.3(mm) x 3.6(mm).