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dc.contributor.authorWang, Terry Tai-Juien_US
dc.contributor.authorGao, Pei-Lingen_US
dc.contributor.authorMa, William Cheng-Yuen_US
dc.contributor.authorKuo, Cheng-Tzuen_US
dc.date.accessioned2014-12-08T15:07:42Z-
dc.date.available2014-12-08T15:07:42Z-
dc.date.issued2010en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://hdl.handle.net/11536/6052-
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.49.06GG15en_US
dc.description.abstractProcesses for fabricating a Ni nanocrystal (NC)-assisted low-temperature polycrystalline silicon thin film transistor (LTPS-TFT) nonvolatile memory device of noble stack below 600 degrees C were successfully developed. The NCs were fabricated in H-plasma atmosphere by heating a nanosized Ni film to realize an appropriate nanoparticle distribution. Results show that NCs with a number density of similar to 5 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge-trapping centers for enhancing the device performance. The results also indicate that the data retentions at the initial time and after 10(4) s for a SiO(2)/Ni-NCs/Si(3)N(4)/SiO(2) gate under the present stack of devices are about 2.2 and similar to 1.1 V, respectively. (C) 2010 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleLow-Temperature Polycrystalline Silicon Thin Film Transistor Nonvolatile Memory Using Ni Nanocrystals as Charge-Trapping Centers Fabricated by Hydrogen Plasma Processen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.49.06GG15en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume49en_US
dc.citation.issue6en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000278966300044-
dc.citation.woscount0-
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