三維繪圖處理器中具消除鋸齒之描畫單元之設計

Abstract

在現今多媒體及虛擬實境的應用上，電腦三維繪圖處理扮演了一個極重要 的角色。近年來，三維繪圖的運用更由原先純科技的範疇，進入一般非科 技的領域。因此，現代三維繪圖之硬體設計不只單純追求高效率及圖像品 質，如何降低成本及系統整合也成為重要的課題之一。在本篇論文中，一 個三維繪圖處理器及其具消除鋸齒功能的描畫單元被設計提出。在系統設 計上，我們利用同一個圖元中資料的平行度來規畫模組，因此可以減少系 統內部匯流排及暫存器的浪費。在描畫單元中，『DDA（數位差分分析式 ）運算單元』及『鋸齒消除單元』是硬體設計上兩個可能造成時間延遲的 關鍵。為了減少時間延遲，我們針對了這兩個單元的特性，提出了架構上 的設計。我們提出『SCRA架構』加速DDA運算單元。在不同長度的加法運 算中，利用運算分割，重組及進位動態擇徑的技巧，這方式可以有效的將 硬體時間延遲縮短到10.51ns (邏輯閘負載0.03pf)，而且能將硬體使用率 提高到92.93%。而在鋸齒消除單元中，我們提出了『次掃描線鋸齒消除』 演算法，在合理的硬體代價下將時間延遲縮短到7.6ns (邏輯閘負載0.03 pf)。在我們三維繪圖處理器所有的設計中，均採用Philips所提供的0.5 um CMOS 的細胞庫。 3-D Computer graphics has played an important role in multimedia and virtual reality systems. Up to the beginning ofthe 1990s, applications of 3-D graphics emerge rapidly from technical areas to non-technical areas. Therefore the goal of state-of-the-art 3-D graphics hardware design not only focus on high performance and quality, but also low cost and system integration. In this thesis, a 3-D graphics processor is proposed to improvethe rendering performance, and the hardware of rasterizationunit with antialiasing capacity is designed. By making use ofthe parallelism in pixel data, the system block of 3-D graphics processor is analyzed to reduce the redundant internal bus routing and registers. The DDA (Digital Differential Analyzer) operation and antialiasing are both the time critical units in the hardware design for rasterization. To improve the time critical condition, we develop two architecture designs: The first is self carry routing adder (SCRA) for DDA operations. The DDA operations suffer the low hardware utilization caused by the various lengths of add operations. By segmentation, rearrangement and dynamic carry routing, The SCRA design can reduce the delay time (10.51ns in 0.03pf load) and raise the hardware utilization (92.93%). The second is the sub- scanline antialiasing algorithm for real-time antialiasing. The delay time is reduced (7.6ns in 0.03pf load) and only moderate area is necessary. All design for this 3-D graphics processor is based on the 0.5 um CMOS cell library of Philips.