标题: 三维绘图处理器中具消除锯齿之描画单元之设计
The Hardware Design for Rasterization with Antialiasing in 3-D Graphics Processor
作者: 梁伯嵩
Liang, Bor-Sung
任建葳
Chein-Wei Jen
电子研究所
关键字: 电脑绘图;消除锯齿;描画单元;三维绘图处理器;Computer Graphics;Antialiasing;Rasterization;3-D Graphics Processor
公开日期: 1995
摘要: 在现今多媒体及虚拟实境的应用上,电脑三维绘图处理扮演了一个极重要
的角色。近年来,三维绘图的运用更由原先纯科技的范畴,进入一般非科
技的领域。因此,现代三维绘图之硬体设计不只单纯追求高效率及图像品
质,如何降低成本及系统整合也成为重要的课题之一。在本篇论文中,一
个三维绘图处理器及其具消除锯齿功能的描画单元被设计提出。在系统设
计上,我们利用同一个图元中资料的平行度来规画模组,因此可以减少系
统内部汇流排及暂存器的浪费。在描画单元中,‘DDA(数位差分分析式
)运算单元’及‘锯齿消除单元’是硬体设计上两个可能造成时间延迟的
关键。为了减少时间延迟,我们针对了这两个单元的特性,提出了架构上
的设计。我们提出‘SCRA架构’加速DDA运算单元。在不同长度的加法运
算中,利用运算分割,重组及进位动态择径的技巧,这方式可以有效的将
硬体时间延迟缩短到10.51ns (逻辑闸负载0.03pf),而且能将硬体使用率
提高到92.93%。而在锯齿消除单元中,我们提出了‘次扫描线锯齿消除’
演算法,在合理的硬体代价下将时间延迟缩短到7.6ns (逻辑闸负载0.03
pf)。在我们三维绘图处理器所有的设计中,均采用Philips所提供的0.5
um CMOS 的细胞库。
3-D Computer graphics has played an important role in
multimedia and virtual reality systems. Up to the beginning
ofthe 1990s, applications of 3-D graphics emerge rapidly from
technical areas to non-technical areas. Therefore the goal of
state-of-the-art 3-D graphics hardware design not only focus on
high performance and quality, but also low cost and system
integration. In this thesis, a 3-D graphics processor is
proposed to improvethe rendering performance, and the hardware
of rasterizationunit with antialiasing capacity is designed. By
making use ofthe parallelism in pixel data, the system block of
3-D graphics processor is analyzed to reduce the redundant
internal bus routing and registers. The DDA (Digital
Differential Analyzer) operation and antialiasing are both the
time critical units in the hardware design for rasterization. To
improve the time critical condition, we develop two architecture
designs: The first is self carry routing adder (SCRA) for DDA
operations. The DDA operations suffer the low hardware
utilization caused by the various lengths of add operations. By
segmentation, rearrangement and dynamic carry routing, The SCRA
design can reduce the delay time (10.51ns in 0.03pf load) and
raise the hardware utilization (92.93%). The second is the sub-
scanline antialiasing algorithm for real-time antialiasing. The
delay time is reduced (7.6ns in 0.03pf load) and only moderate
area is necessary. All design for this 3-D graphics processor is
based on the 0.5 um CMOS cell library of Philips.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT840430006
http://hdl.handle.net/11536/60603
显示于类别:Thesis