一個 2 伏特 2 G 赫茲的 CMOS 相鎖迴路

Abstract

本篇論文描述 2 伏特 2 G 赫茲的相鎖迴路積體電路,它包含電壓控制振 盪器 (Voltage Controled Oscillator),多係數除頻器 (Multi-Modulus Divider),相頻偵測器 (Phase-Frequency Detector),和電荷充式濾波器 (Charge-Pump Filter). 電壓控制振盪器為負電阻電感電容的射頻振盪器,其振盪頻率是由可調式 電容所控制,輸出頻率從 1.9 GHz 到 2 GHz .電流模式非同步多係數除頻 器可除頻倍數從 128 到 256,共 32 個除數.一個重新同步的電路是為了 降低非同步除頻器從第一級到最後一級,因為傳輸延遲所造成的相位雜訊 而設計的.相頻偵測器比較輸入參考信號與除頻器除頻後信號的相位及頻 率差,輸出充電 UP 和放電 DN 的數位信號,電荷充式濾波器將相頻偵測器 的數位輸出,轉換成電壓控制振盪器所能接受的類比輸入訊號,以控制振盪 器的輸出頻率.本論文所有的數位電路是由改良型電流模式邏輯構成,以減 小電壓源雜訊的影響. 這個相鎖迴路是用 0.6um SPDM CMOS 的單晶製程製造,此積體電路包含 pads 所用面積共 3mm*3mm,當工作在電壓 -2V 且最大輸出頻率 2GHz 時, 總消耗功率是 154mW. This thesis describes the design of a 2V 2GHz phase-locked loop (PLL) which is consisted of a voltage-control oscillator (VCO), a multi-modulusdivider (MDIV), a phase-frequency detector (PFD), and a charge-pump filter (CPF). The VCO is a LC-tuned negative-resistance oscillator. The frequency is adjusted through a simulated-varactor circuit, and can vary from 1.9 GHz to 2.0 GHz. The multi-modulus divider has 32 different divide ratio, ranging from 128 to 256. A re- synchronizing circuit is included in the divider to minimize phase jitter. The phase-frequency detector compares the phase of the divider output with that of a reference input, and controls the charging and discharging of the charge pump filter. All the digital circuits are implemented with current-mode logic to minimize power noise. The PLL has been implemented in a 0.6 um SPDM CMOS technology. The totalchip size is 3mm*3mm, including pads. Operating from a single -2V supply, the maximum output frequency is 2GHz. The total power consumption is 154mW.