供數位 64-QAM 及 8-VSB 載波再生電路設計與實作

Abstract

在本論文中, 我們提出一種可使用在數位64 QAM及8 VSB解調器中的載 波再生架構,完成其數學與效能分析,對於不同通道模型與訊號雜訊比作詳 盡的模擬和討論,並且自製出一套數位化載波再生電路來驗證其可行性與 效能. In this thesis, we propose an architecture for carrier recovery in both64 QAM and 8 VSB Modems. We have complete mathematical analysis and performanceevaluation. Also, we simulate and discuss our archiecture in different channelmodels and signal-to-noise ratios. And a digitized carrier-recovery circuit isimplemented to prove the feasibility of our architecture.