标题: 低温制造高性能复晶矽薄膜电晶体
Low-Temperature Fabricated Polycrystalline Silicon Thin-Film Transistors
作者: 林孝义
Lin, Hsiao-Yi
张俊彦, 雷添福
Chun-Yen Chang, Tan Fu Lei
电子研究所
关键字: 复晶矽薄膜电晶体;化学机械研磨;低温;电浆钝化;热载子;磁感测器;Poly-Si;CMP;Low-temperature;Plasma passivation;Hot carrier;Magnetic sensors
公开日期: 1996
摘要: 增大复晶矽晶粒与提高晶粒品质之技术常用来改善复晶矽薄膜电晶体的特
性,实验中以具有极低背景与成长压力的超高真空化学气相沉积系统成长
高品质的复晶矽薄膜,由于此系统成长的薄膜即为复晶矽故不需雷射或炉
管等退火处理步骤,但表面粗糙度却因晶粒的结晶方向之不同而变得很大
使其不适合用于制作顶闸极薄膜电晶体,于是我们提出以化学机械研磨法
抛光复晶矽而成功研制出高性能复晶矽薄膜电晶体,p与n通道载子移动率
分别达58 cm2/V-s与98 cm2/V-s,临界电压值均小于0.6 V;接着配合电
浆辅助化学气相沉积系统以四乙基环氧矽化物(TEOS)与氧(O2)为反应气体
成长闸极氧化层,虽然这不是目前最好的选择,但我们仍研制出n通道载
子移动率达46 cm2/V-s,临界电压值小于0.8 V的低温(£ 550°C)与低热
预算之复晶矽薄膜电晶体。另项实验则以矽乙烯(Si2H6)作为低压化学气
相沉积的气体成长非晶矽膜再经炉管退火成较大晶粒(~1 mm)的复晶矽薄
膜,这是因为以Si2H6沉积的非晶矽乱度较大,但其结晶时间亦较长,结
晶潜伏期也较长,以此材料制成的低温(£ 600°C)复晶矽薄膜电晶体,p
与n通道载子移动率分别达36 cm2/V-s与68 cm2/V-s,临界电压均分别小
于-1.3 V与0.08 V;对于论文中所研制的复晶矽薄膜电晶体均经过氨气或
氮气电浆的钝化处理,我们发现钝化处理对于以Si2H6沉积的p通道复晶矽
薄膜电晶体之特性(如载子移动率与临界电压)改善不大,进一步藉由活化
能分析费米能阶的位置发现在氨气钝化处理前此复晶矽略呈p型,这和一
般以矽烷(SiH4)沉积的膜相同,但钝化处理后却略呈n型,正好和一般以
SiH4沉积的膜相反,我们认为这是氮原子除了钝化作用外所产生的予体掺
杂效果,在一般以SiH4沉积的复晶膜中之所以没发现是因为其晶粒较
小(0.2~0.3 mm),晶粒边界的析离作用减低了氮原子的掺杂效果;此外并
发现氮比氨电浆处理后之热载子可靠度更佳,这是因氮电浆钝化后在复晶
矽中只形成键结较强的矽氮键而没有键结较弱的矽氢键。最后根据现有的
单一能陷解析模型为基础扩展晶粒边界的载子捕捉模型至次临界工作区,
以及漏电流区的电场辐射能陷辅助穿遂模型加上能带至能带穿遂模型,再
修改晶粒边界调变模型,我们可以准确地配适各操作区的元件特性。附录
部分是关于半导体霍尔磁场感测元件的制作,我们提出在晶片背面镀磁性
材料的方法将元件的磁场感测灵敏度提升了一个数量级,并且没有磁滞的
现象产生,据此我们进一步把这个观念应用在三度空间的磁场感测元件,
用以改善垂直晶片表面的灵敏度,因此仅利用最简单的结构便成功地在三
个轴向得到相当对称的感测灵敏度,此外也利用在电流注入端蚀刻环绕沟
槽来抑制交越灵敏度,此交越灵敏度仅为1.3%。
The increase in the grain size and the deposition of high
quality films are commonly carried out to improve the
characteristics of polycrystalline silicon (poly-Si) thin film
transistors (TFTs). An ultrahigh vacuum chemical vapor
deposition (UHV/CVD) system with very low base and deposition
pressures was used to deposit high quality poly-Si films. Due to
the as-deposited poly-Si films, laser or furnace anneal is not
necessary. However, the grain growth rate is dependent on the
orientation, which results in very rough surface and makes top-
gate TFTs unsuitable. Chemical mechanical polish (CMP) technique
was proposed to planarize the surface of poly-Si for fabrication
of high performance poly-Si TFTs. The carrier mobilities for p-
and n-channel devices are 58 cm2/V-s and 98 cm2/V-s,
respectively, the threshold voltage values are below 0.6 V;
Then, tetra-ethyl-ortho-silicate (TEOS) and oxygen (O2) mixture
was used to deposit gate oxide by plasma-enhanced chemical vapor
deposition (PECVD). Even though such a method is not the best
technology, the field effect mobility of 46 cm2/V-s and
threshold voltage below 0.8 V were obtained for n-channel poly-
Si TFTs with low temperature (£550°C) and low thermal budget
processes. In another study, disilane (Si2H6) gas was used to
deposit amorphous silicon (a-Si) films by low-pressure chemical
vapor deposition (LPCVD). Then, a-Si films were transferred to
poly-Si films with larger grain size (~1 mm). The larger grain
size is due to the higher disorder in these a-Si films. However,
the crystallization time and incubation time is also longer. The
Low temperature process poly-Si TFTs fabricated using Si2H6 have
mobilities of 36 cm2/V-s and 68 cm2/V-s, and threshold voltages
of -1.3 V and 0.08 V for p- and n-channel devices, respectively;
All devices were passivated by NH3 or N2 plasma. It was found
that improvement (mobility and threshold voltage) of p-channel
devices deposited using Si2H6 is minor. By leakage activation
energy to determine the Fermi level before NH3 plasma treatment,
it was found that the same as that of the silane (SiH4)
deposited films, these films are slightly p-type. But after
plasma passivation, these films are slightly n-type, which is
opposite to that of SiH4 deposited films. It is believed that
not only the N passivation effect but also donor doping effect
plays important role. The effect was not found in SiH4 deposited
films due to their smaller grain size (0.2~0.3 mm) and the
higher grain boundary segregation effect, which suppresses
nitrogen doping effect. Beside, it was found that nitrogen
passivated devices have better hot carrier endurance than
ammonia passivated ones. The reason is that there are only
stronger Si-N bonds and no weaker Si-H bonds in nitrogen treated
devices. Finally, based on present single-trap grain boundary
trapping model on above threshold region, we extended the model
to subthreshold region. In leakage region, field-enhanced trap-
assisted tunneling and band-to-band tunneling models were
considered. Then, modified grain boundary modulation model was
taken into account. We can accurately simulate device
characteristics on all operation regions. Fabrication of Hall
semiconductor magnetic devices is appended in Appendix. Magnetic
materials coated on the backside of wafers were proposed to
improve the sensitivity by one order of magnitude without
magnetic hysteresis was found. Further, the idea was applied to
three-dimensional magnetic sensors to improve the sensitivity
perpendicular to chip plane. Therefore, we have successfully
obtained the symmetry sensitivities in three axis directions
using the simplest structure. Beside, the surrounding trench
near the current input terminal is used to suppress the cross
sensitivity. The cross sensitivity is only 1.3%.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT850428008
http://hdl.handle.net/11536/61871
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