低溫製造高性能複晶矽薄膜電晶體

Abstract

增大複晶矽晶粒與提高晶粒品質之技術常用來改善複晶矽薄膜電晶體的特 性，實驗中以具有極低背景與成長壓力的超高真空化學氣相沉積系統成長 高品質的複晶矽薄膜，由於此系統成長的薄膜即為複晶矽故不需雷射或爐 管等退火處理步驟，但表面粗糙度卻因晶粒的結晶方向之不同而變得很大 使其不適合用於製作頂閘極薄膜電晶體，於是我們提出以化學機械研磨法 拋光複晶矽而成功研製出高性能複晶矽薄膜電晶體，p與n通道載子移動率 分別達58 cm2/V-s與98 cm2/V-s，臨界電壓值均小於0.6 V；接著配合電 漿輔助化學氣相沉積系統以四乙基環氧矽化物(TEOS)與氧(O2)為反應氣體 成長閘極氧化層，雖然這不是目前最好的選擇，但我們仍研製出n通道載 子移動率達46 cm2/V-s，臨界電壓值小於0.8 V的低溫(£ 550°C)與低熱 預算之複晶矽薄膜電晶體。另項實驗則以矽乙烯(Si2H6)作為低壓化學氣 相沉積的氣體成長非晶矽膜再經爐管退火成較大晶粒(~1 mm)的複晶矽薄 膜，這是因為以Si2H6沉積的非晶矽亂度較大，但其結晶時間亦較長，結 晶潛伏期也較長，以此材料製成的低溫(£ 600°C)複晶矽薄膜電晶體，p 與n通道載子移動率分別達36 cm2/V-s與68 cm2/V-s，臨界電壓均分別小 於-1.3 V與0.08 V；對於論文中所研製的複晶矽薄膜電晶體均經過氨氣或 氮氣電漿的鈍化處理，我們發現鈍化處理對於以Si2H6沉積的p通道複晶矽 薄膜電晶體之特性(如載子移動率與臨界電壓)改善不大，進一步藉由活化 能分析費米能階的位置發現在氨氣鈍化處理前此複晶矽略呈p型，這和一 般以矽烷(SiH4)沉積的膜相同，但鈍化處理後卻略呈n型，正好和一般以 SiH4沉積的膜相反，我們認為這是氮原子除了鈍化作用外所產生的予體摻 雜效果，在一般以SiH4沉積的複晶膜中之所以沒發現是因為其晶粒較 小(0.2~0.3 mm)，晶粒邊界的析離作用減低了氮原子的摻雜效果；此外並 發現氮比氨電漿處理後之熱載子可靠度更佳，這是因氮電漿鈍化後在複晶 矽中只形成鍵結較強的矽氮鍵而沒有鍵結較弱的矽氫鍵。最後根據現有的 單一能陷解析模型為基礎擴展晶粒邊界的載子捕捉模型至次臨界工作區， 以及漏電流區的電場輻射能陷輔助穿遂模型加上能帶至能帶穿遂模型，再 修改晶粒邊界調變模型，我們可以準確地配適各操作區的元件特性。附錄 部分是關於半導體霍爾磁場感測元件的製作，我們提出在晶片背面鍍磁性 材料的方法將元件的磁場感測靈敏度提升了一個數量級，並且沒有磁滯的 現象產生，據此我們進一步把這個觀念應用在三度空間的磁場感測元件， 用以改善垂直晶片表面的靈敏度，因此僅利用最簡單的結構便成功地在三 個軸向得到相當對稱的感測靈敏度，此外也利用在電流注入端蝕刻環繞溝 槽來抑制交越靈敏度，此交越靈敏度僅為1.3%。 The increase in the grain size and the deposition of high quality films are commonly carried out to improve the characteristics of polycrystalline silicon (poly-Si) thin film transistors (TFTs). An ultrahigh vacuum chemical vapor deposition (UHV/CVD) system with very low base and deposition pressures was used to deposit high quality poly-Si films. Due to the as-deposited poly-Si films, laser or furnace anneal is not necessary. However, the grain growth rate is dependent on the orientation, which results in very rough surface and makes top- gate TFTs unsuitable. Chemical mechanical polish (CMP) technique was proposed to planarize the surface of poly-Si for fabrication of high performance poly-Si TFTs. The carrier mobilities for p- and n-channel devices are 58 cm2/V-s and 98 cm2/V-s, respectively, the threshold voltage values are below 0.6 V; Then, tetra-ethyl-ortho-silicate (TEOS) and oxygen (O2) mixture was used to deposit gate oxide by plasma-enhanced chemical vapor deposition (PECVD). Even though such a method is not the best technology, the field effect mobility of 46 cm2/V-s and threshold voltage below 0.8 V were obtained for n-channel poly- Si TFTs with low temperature (£550°C) and low thermal budget processes. In another study, disilane (Si2H6) gas was used to deposit amorphous silicon (a-Si) films by low-pressure chemical vapor deposition (LPCVD). Then, a-Si films were transferred to poly-Si films with larger grain size (~1 mm). The larger grain size is due to the higher disorder in these a-Si films. However, the crystallization time and incubation time is also longer. The Low temperature process poly-Si TFTs fabricated using Si2H6 have mobilities of 36 cm2/V-s and 68 cm2/V-s, and threshold voltages of -1.3 V and 0.08 V for p- and n-channel devices, respectively; All devices were passivated by NH3 or N2 plasma. It was found that improvement (mobility and threshold voltage) of p-channel devices deposited using Si2H6 is minor. By leakage activation energy to determine the Fermi level before NH3 plasma treatment, it was found that the same as that of the silane (SiH4) deposited films, these films are slightly p-type. But after plasma passivation, these films are slightly n-type, which is opposite to that of SiH4 deposited films. It is believed that not only the N passivation effect but also donor doping effect plays important role. The effect was not found in SiH4 deposited films due to their smaller grain size (0.2~0.3 mm) and the higher grain boundary segregation effect, which suppresses nitrogen doping effect. Beside, it was found that nitrogen passivated devices have better hot carrier endurance than ammonia passivated ones. The reason is that there are only stronger Si-N bonds and no weaker Si-H bonds in nitrogen treated devices. Finally, based on present single-trap grain boundary trapping model on above threshold region, we extended the model to subthreshold region. In leakage region, field-enhanced trap- assisted tunneling and band-to-band tunneling models were considered. Then, modified grain boundary modulation model was taken into account. We can accurately simulate device characteristics on all operation regions. Fabrication of Hall semiconductor magnetic devices is appended in Appendix. Magnetic materials coated on the backside of wafers were proposed to improve the sensitivity by one order of magnitude without magnetic hysteresis was found. Further, the idea was applied to three-dimensional magnetic sensors to improve the sensitivity perpendicular to chip plane. Therefore, we have successfully obtained the symmetry sensitivities in three axis directions using the simplest structure. Beside, the surrounding trench near the current input terminal is used to suppress the cross sensitivity. The cross sensitivity is only 1.3%.