利用暫態電流量測技術研究超大型積體電路元件中氧化層之可靠度

Abstract

電性stress引發之氧化層可靠度問題已在深次微米超大型積體電路技術領 域中引起廣泛討論。本論文將針對五項可靠度主題進行研究。首先，吾人 利用一套完整之熱能與電場激發模式，模擬金氧半元件在OFF狀態之漏電 流效應。在此模式中，漏電途徑係電洞由界面缺陷跳至共價帶，電子由缺 陷跳至傳導帶。無論電洞發射或電子發射均可經由量子穿隧或熱能激發而 完成。根據吾人研究結果顯示，當汲極至閘極電壓（Vdg）很大時，汲極 漏電流主要藉能帶-缺陷-能帶二階穿隧完成；隨著Vdg逐漸減小，熱能-電 場激發乃成為主要漏電流機制；當Vdg很小時，則以SRH理論所預期之熱能 激 Electrical stress induced oxide reliability issues have received considerable interest in deep submicron VLSI technology. In this dissertation, five reliability research topics have been studied. First, an interface trap induced drain leakage current in an off-state MOSFET was characterized by a complete thermionic and field emission model. In the model, a complete band-trap-band leakage path is formed at the Si/SiO2 interface by hole emission from interface traps to a valence band and electron emission fro