電漿製程對超薄氧化層損害效應之研究

Abstract

電漿製程的損害效應對於超大型積體電路中元件之可靠度之衝擊，已 逐漸成為一重要課題。本論文依此而研究電漿蝕刻對元件造成損害效應之 評估，分成以下兩部份。 第一部份，將研究MERIE電漿蝕刻機台及其 隨後之光阻灰化過程對閘極氧化層造成之損傷程度。 測試元件分成兩種 ：電容器與N型金氧半電晶體。Qbd及 IETR 這兩個指標用來偵測電漿損害 效應之嚴重性。 結果證實IETR是比較有效率的。但是對於氧化層厚度薄 於60*的元件而言，由於電子捕捉現象並不明顯，所以Qbd成為唯一的指標 。另外，對於電晶體而言，除了上述兩種方法之外，熱載子施壓及 Fowler-Nordheim 穿遂施壓也用來檢測元件之可靠度分析。綜合結果，晶 片邊緣之氧化層比中心區域遭受較多的電漿損害。 第二部份，將探討 下吹式灰化機台中和光阻相關的損害現象。經證實，在光阻灰化過程中， 沒有覆蓋光阻的元件， 即使當天線面積比由16上升到104，且氧化層厚度 僅42*，元件僅遭受到少量的電漿損害。相反地，對於有覆蓋光阻的元件 ，在同樣厚度且天線面積比為104之下，卻顯示晶片中心區域的元件已受 到嚴重電漿損害。對此，提出一個等效電路模型解釋這個有趣的現象。 另外，電晶體之參數轉移電導閘極漏電也得到相同的結果。 最後，以一 個新方法CHARM晶片技術直接地測出晶片表面與基座間之電位差，亦獲得 亦獲得相同的驗證。 Plasma charging induced damage in ultra-thin oxide is increasingly becoming a serious concern because of its impact on the devices reliability in ULSI applications. The thesis is reported about evaluation of damage effects on devices resulted from plasma etching and is introduced following in two parts. Firstly, gate oxide damage induced by plasma charging during metal etching with magnetic-enhanced reactive ion etching (MERIE) and subsequent ashing was investigated. Both capacitors and N-MOSFETs were employed as the test vehicles. For capacitors, charge-to-breakdown (Qbd) and initial electron trapping slope (IETS) techniques were employed to characterize the plasma charging induced gate oxide damage. Our results indicated that the IETS technique was much more efficient in characterizing the damage. However, due to reduced electron trapping for oxide thinner than 60□ Qbd became the only viable technique. For transistor test structure, hot carrier stress and Fowler-Nordheim tunneling stress were applied to study the transistor reliabilities. The results showed that devices located at the edge region of the wafer suffered more severe damage than those located at the central region for both the capacitor and transistor test structures. Secondly, resist- related damage on ultra-thin gate oxide during plasma ashing was investigated. Capacitors and transistors were again applied as the test keys to reveal the resist-related damage. It was found surprisingly that capacitors without resist covering during plasma ashing depicted only minor damage, even when oxide is as thin as 42□and the area ratio is as large as 104. In contrast, capacitors with resist covering suffered more severe degradation from plasma charging, even when oxide is as thick as 60□ An equivalent circuit model was proposed to explain this interesting and surprising phenomenon. Transistor parameters, such as linear transconductance (Gm), gate leakage current (Ig at Vg=Vth), were measured on the test structures. These results also depicted quite similar trends to those found in the capacitor test structures. To further confirm our model, we also employed the CHARM wafer to directly measure the potential difference between the wafer surface and the substrate. The CHARM results again confirmed our hypothesis.