閘極氧化層在電漿蝕刻中的損害研究

Abstract

在極大型積體電路製程中,薄閘極氧化層遭受之電漿電荷損傷因直接對元 件可靠度造成嚴重影響,已逐漸成為一重要課題.本論文乃藉由不同邊長之 測試天線結構,探討在閘極電漿蝕刻製程中產生的閘極氧化層電荷累積損 傷現象.電漿蝕刻所造成的損傷包括過大的閘極漏電流,以及崩潰電場的降 低.研究結果顯示,閘極氧化層電荷損傷會隨著天線邊長的增加而遞增.此 外, 閘極氧化層厚度為6nm的金氧半電容對電漿損傷的容忍度比閘極氧化 層厚度為9.5nm與1.45nm者更差.氧化層薄膜電性退化可由矽與二氧化矽界 面能態密度增加來加以解釋.最後,我們發現閘極氧化層會因閘極摻雜濃度 的增加而遭受更大的損傷.同時提出電路模型以解釋在電漿損傷中,閘極摻 雜濃度所造成的影響. Plasma charge-induced damages to thin gate oxides are increasingly becoming serious topics because they directly impact device reliabilityin ultra-large-scale-integrated circuits.In this thesis,poly gate plasmaetching,has been studied using test antenna structures with various peripheral lengths. The observed damages by plasma etching include the excessive gate leakage current and a degradation in breakdown field. Theresults indicate that gate oxide charging damage increases with the increasing of the antenna peripheral length.In addition,the MOS capacitors with gate oxide of 6nm exhibits worse endurance to plasma damage than those of 9.5nm and 14.5nm. The increase of interface state density at theSi/SiO2 interface was correlated well with the measured electrical degradation of the oxide films.Finally,we have found that gate oxidesuffered more damage with an increase in poly doping level for dry- etchedsamples and a circuit model was proposed to demonstrate the role of polydoping levels plasma damage.