快閃電擦可程式唯讀記憶體元件的分析及設計

Abstract

在本文中,我們對於快閃電擦可程式唯讀記憶元件的儲存及抹除記憶 特性提出了理論上的分析並做實驗上的探討.基於耦合係數的觀念,本文提 出此一元件模型做為儲存及抹除記憶動作的描述,並對於儲存/記憶之效率 及持續力做一詳細的討論及剖析.經由此一模型,電流及耦合係數能被模擬 出來.在適當地調整耦合係數過程中,模擬出來的閘極電流和實驗值十分吻 合.此外,本文也利用一個二維金氧半元件模擬器(SUMMOS)來模擬週邊N-通 道淺攙雜汲極金氧半場效電晶體,並且粹取相關元件參數.經由此模型分析 及參數粹取技巧,可改進元件的設計來達到高效率及高可靠度的應用. Theoretical modeling and experimental analysis for flash EEPROM are presentedin this thesis. The device model is given based on the concept of coupling ratios. Programming and erasing operations are adequately represented by this device model, and a detailed study on both programming/erasing efficiency andcycling endurance are made and analyzed. By use of this model, the gate currentand coupling ratios can be well simulated. By appropriately adjusting the coupling ratios, good agreements are then achieved between the simulated and experimental results. A 2-D MOS device simulator(SUMMOS) is used to simulate experimental peripheral LDD N-MOSFETs and to extract device parameters. Based on this model and extraction techniques, we can improve flash EEPROM design forhigh performance and excellent reliability applications.