5.5GHz 低功耗射頻 CMOS混頻器設計與研製

Abstract

本篇論文介紹低功率消耗之無線區域網路之射頻吉伯特混波(Gilbert mixer) 之電路設計。對於單晶片(SoC)手持式無線網路之產品應用，低功率消耗之電子式產品，以蔚為新的潮流及趨勢。本論文是以TSMC 0.18μm 1P6M CMOS model 模擬電路及實現低功率電路。主要電路是以吉伯特混波器(Gilbert mixer)為主，電源供應系利用LC並聯諧振電路當作RF-MOS級LO MOS電源供應。吉伯特混波器基本架構圖以multi-gate電路放大器，其主要功能有二：第一為增加Gm值，以增加其增益轉換值(S21)；第二增加其線性度，利用不同之輸入閘級電壓，將非線性的部分做部分的互相抵銷，使其線性度增加。在閘級輸入電壓串聯一電感目的為使輸入信號的能量集中在閘及輸入端作為阻抗匹配，使其有最大的能量轉換。並適當的嘗試改變基本電路架構於射頻輸出端與LO間加入一電感，可得到更大的轉換增益(Conversion Gain)。我們亦嘗試在IF輸出端並聯一被動元件-電容，以增加其線性度。本合成器在實際封裝量測中，輸出 P-1dB 點為2.5 dBm，IIP3為11dBm即轉換增益為7.46 dB，消耗功率為9.5 mW。

This thesis proposes a low-power mixer circuit design for wireless communication applications. For systems-on-a-chip (SoC) in portable wireless networks, low power requirement is increasingly important. In this study, TSMC 0.18μm 1P6M CMOS process and model are employed for circuit implementation and simulation to achieve low power. Gilbert cell mixer circuit is adopted and some new ideas are proposed to reduce power consumption. The proposed new ideas cover a parallel resonator realized by LC-tanks and multi-stage parallel RC networks for linearity improvement. Also, multi-gated structure is applied in the RF input as a transconductance amplifier to improve conversion gain and linearity . The higher conversion gain (S21) is due to larger Gm. The better linearity of higher IIP3 is attributed to third-order nonlinear term cancellation realized by gate bias tuning on the multi-gated structure. An on-chip inductor is added in RF input for impedance matching. For LO input impedance matching, off-chip inductor is employed. For RF output a pair of on-chip inductors were used to increase conversion gain. The parallel R-C networks add to IF output terminal can improver linearity with higher IIP3. Measured performance in terms of linearity is P-1dB at 2.5 dBm and IIP3 at 11 dBm The conversion gain can be achieved at 7.46 dB, and power consumption can be maintained as low as 9.5 mW.