嵌入式數位信號處理器之硬體模擬與系統原型創建

Abstract

在嵌入式數位信號處理器的開發過程中，驗證數位信號處理器功能的正確性是非常重要的一個步驟，且通常會花費掉許多的時間。要正確的完成數位信號處理器的驗證，設計者可以使用軟體模擬、正規化驗證或是硬體模擬等方法來完成。遺憾的是，軟體模擬對於模擬時間這點來說是一種非常沒有效率的方法，正規化驗證能縮短驗證時間但無法驗證大型的電路，而使用硬體模擬雖然可以快速的模擬複雜電路，但其缺點是缺乏偵錯能力。在這篇論文裡我們是用硬體模擬的方法來縮短信號處理器的驗證與開發時程。為了克服硬體模擬器缺乏偵錯能力的缺點，我們提出了一種新的嵌入式模擬器架構，這種架構透過數位信號處理器本身的硬體來減少驗證所需要的時間，同時利用數位信號處理器的指令集和硬體中斷來減少額外的偵錯硬體。我們將這個模擬器模組整合到一個數位訊號處理器–Pica DSP (Packed Instruction and Cluster Architecture)並且藉由FPGA完成Pica DSP的系統原型創建與驗證。模擬及實作的結果顯示整合嵌入式模擬器後的數位信號處理器可以容易的被驗證與偵錯，而且整合後硬體增加1.53%。

In the development procedure of embedded DSP, to verify the functionality of DSP is a very important step and it usually takes a lot of time. Designers can use software simulation, formal verification, or hardware emulation to complete the verification of DSP. Unfortunately, software simulation is a very inefficient way considering the simulation time. Formal verification could shorten verification time, but can’t handle large-scale circuitry. Although hardware emulation could emulate complex circuitry, its shortcoming is the lack of debugging ability. In this thesis, we use hardware emulation to shorten the development procedure of DSP. In order to overcome the shortcoming of hardware emulator - the lack of debugging ability, we propose a new embedded In-Circuit Emulator (ICE) architecture, in which we use DSP ready-made hardware to reduce the time demand of verification. At the same time, we use the instruction set and hardware interrupts of DSP to reduce extra debugging hardware. We integrate this emulator into a DSP – Pica DSP (Packed Instruction and Cluster Architecture). We also rely on FPGA to implement and verify the system prototype of Pica DSP. The result of implementation shows that Pica DSP integrates ICE could be easily verified and debugged. The hardware overhead of Pica DSP is 1.53% after we integrate embedded ICE.