完整後設資料紀錄
DC 欄位語言
dc.contributor.author唐伯元en_US
dc.contributor.authorPo-Yuan Tangen_US
dc.contributor.author郭浩中en_US
dc.contributor.authorHao-Chung Kuoen_US
dc.date.accessioned2014-12-12T02:19:21Z-
dc.date.available2014-12-12T02:19:21Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009167510en_US
dc.identifier.urihttp://hdl.handle.net/11536/63368-
dc.description.abstract追求低電壓產品的使用操作,不僅能降低功率的損耗,更能確保產品的可靠度,延長產品的使用壽命. 因SRAM在低電壓下操作時,不是遇到“寫”的問題,就是遇到“讀”的問題.故要使之能在低電壓下有效的工作,則非要能同時解決這兩種問題不可. 本實驗中所引用之SRAM,則是故意將SRAM Cell設計成擁有較高的SNM,使之比較偏向不會有讀的問題,然後利用在寫時,將寫入的資料設計成比0 伏特還來的低的電壓(為負電壓),借此增加寫入的能力.當然因SRAM Cell已被偏向讀的一方,故在低電壓下所面臨之寫的問題,會比原先未被偏向讀的特性還來得嚴重,故此負電壓必須能夠補償及克服此寫的問題才行.同時,也利用降低SRAM Cell的電壓,藉以降低存“1”的能力.更增加寫入的成功. 除了在寫時加強外,本實驗還提出了在低電壓下,增加讀速度的改善方法.那就是利用與產生負電壓同一個電壓產生器,來產生一個比外面單一輸入電壓源還來得高的電壓值,藉以增加讀的電流.(在本實驗中模擬VDD=0.5v,卻有約0.7v的讀出電流).故可同時達到低電壓,低漏電,低功率消耗與高效能之目的. 而事實上,在高壓下操作時是沒有任何寫或讀的問題,故在本實驗中也設計了在高壓下,將此電壓產生器“關掉”的裝置,如此可減少在高壓下有多餘的功率消耗,又可避免產生太低的負電壓或太高的正電壓而造成產品的可靠度問題. 本文將針對以上設計來加以特性上的探討,尤其是在低電壓下操作.zh_TW
dc.description.abstractSearching for the lower voltage operation not only can reduce the power consumption but also can extend the life time because of improving the reliability issue. Only two issues that make SRAM cannot work at low voltage, write or read issue or both. So it needs to improve these two at the same time when do low voltage operation. In this thesis, first to bias SRAM Cell to have higher SNM, let it doesn’t have read problem and then using negative voltage to write data to improve write ability. Since Cell is biased to prefer read, the write problem should be worse than original design. So it needs to cover back this write issue using negative design. At the same time, also reduce the Cell power to reduce the keep “1” node ability. Not only get improvement at write cycle, but also pump Cell power at read cycle to improve the read performance at low voltage operation using the same voltage generator as negative voltage generator. (In this thesis, the simulation showed 0.7v read current at VDD =0.5v). So we can get both low voltage/low leakage and high performance together. In fact, there is no any write and read issue at high voltage operation. So I have a shut off design in this thesis when do high voltage operation, in order to get less active power consumption and prevent reliability problem caused by too large negative/positive voltage. I will have more evaluation in this thesis especially at low voltage operation.en_US
dc.language.isozh_TWen_US
dc.subject低功率zh_TW
dc.subject低電壓zh_TW
dc.subject靜態記憶體zh_TW
dc.subject負電壓寫入zh_TW
dc.subject正電壓讀出zh_TW
dc.subjectLow Poweren_US
dc.subjectLow voltageen_US
dc.subjectSRAMen_US
dc.subjectNegative Voltage Writeen_US
dc.subjectPumping Voltage Readen_US
dc.title利用電路設計技巧達到低電壓低功率消耗之靜態記憶體操作zh_TW
dc.titleDesign Assist Method to Achieve Low Voltage Low Power SRAM Operationen_US
dc.typeThesisen_US
dc.contributor.department電機學院電子與光電學程zh_TW
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