低相位雜訊架構之ku頻段鎖相震盪器

Abstract

本論文研製低相位雜訊之Ku頻段鎖相震盪器。主要分為兩部份，第一部份使用一般直接除頻架構之鎖相迴路來實現鎖相震盪器。第二部份使用混波器取代直接除頻架構中之除頻器來實現鎖相震盪器。利用混波器相位雜訊之特性來取代除頻器以降低整個迴路的除頻比例，藉此來改善輸出端之相位雜訊。兩種架構之電路同時被分析並實現。本論文測試結果顯示使用混波器取代直接除頻架構中之除頻器之架構於15.2 GHz距離載波100KHz之相位雜訊為-106.33 dBc/Hz，此結果優於直接除頻架構，以本論文所測試結果，相位雜訊能夠改善8.84 dB。

The thesis is low phase noise architecture study of a Ku band phase locked oscillator. The content is divided into two parts. In section 1, the general direct division architecture is used to implement phase locked oscillator (PLO). In section 2, mixer is used to replace frequency divider in general architecture. Using mixer to replace frequency divider can reduce the frequency division ratio and improve output phase noise performance. Two kinds of architectures are analyzed and produced. The test results show that using mixer to replace frequency divider can improve the output phase noise. The phase noise at 15.2 GHz offset carrier 100 KHz is –106.33 dBc/Hz. It is 8.84 dB better than the direct division architecture.