X86 超純量微處理機之加強型相依性指令視窗

Abstract

超純量(Superscalar)技術已被廣泛地運用在現今的高效能微處理機上。由於超純量微處理機可同時解碼多道指令且具備較多的指令執行單元, 因此指令視窗(Instruction Window)必須能夠由解碼器接受多道指令並且由選擇邏輯(Selection Logic)選擇多道指令送往指令執行單元執行。 這表示在未來的微處理機設計上, 提昇指令視窗效能之研究顯得越來越重要。 在本篇論文中, 我們針對以相依性指令視窗, 先進先出緩衝器(FIFO Buffers), 提出兩個增進指令視窗之效能的方法: 一. 我們改變原本先進先出緩衝器的選擇邏輯 - 固定優先順序(Fixed Priority), 而以其他三種選擇邏輯取代之。 這三種選擇邏輯分別是: (1) 考慮最大相依性(Maximum Dependence), (2) 考慮鏈長(Chain Length), (3)綜合考慮最大相依性及鏈長。 實驗結果顯示, 這三種選擇邏輯都較原本的選擇邏輯為佳。 若是考慮硬體實作成本, 則以考慮鏈長為最適當之選擇邏輯。 二. 我們增加一個緩衝器與先進先出緩衝器併用而做為指令視窗,這個緩衝器的功能類似一個小型的集中式指令視窗(Centralized Instruction Window), 因此名為指令視窗緩衝器(Instruction Window Buffer, IWB) 。 指令視窗緩衝器容量甚小, 大約僅需存 1~4 個指令。 我們設定存放在指令視窗緩衝器的指令必須是其運算元都已就緒(Ready)的指令。 因此, 我們也修改引導邏輯(Steering Logic) 。 最後, 我們合併這兩種增進指令視窗之效能的方法來加強先進先出緩衝器。在總項目(Entry)較大的情況之下, 改善後的先進先出緩衝器比採用集中式指令視窗的效能還要好。

Today, superscalar technique is widely applied to high-performance microprocessors. Because multiple instructions are decoded and more functional units are employed, the instruction window must accept more instructions from the decoder and its selection logic must select multiple instructions for execution. Therefore, the enhancement of instruction window is more and more important for designing high-performance microprocessors in the future. In this thesis, we propose two strategies to enhance the performance of dependent-based instruction window, i.e. ,FIFO Buffers. The two strategies are described as follows: 1. We replace the original selection logic of FIFO Buffers, fixed priority, by other three kinds of selection logic. The three selection logic are maximum dependence, chain length, and both (maximum dependence, chain length). The simulation results show that anyone of the three selection logic performs better than the original one. If consider the hardware cost for implementation, then the chain length is the proper selection logic. 2. We add another buffer associated with the FIFO Buffers as the instruction window. The additional buffer performs as a small centralized instruction window, and thus we called it instruction window buffer (IWB). The IWB may be very small for keeping only one to four instructions. We enforce that the IWB may keep only the ready instructions, i.e. ,all of their operands are ready. We modify the steering logic of the FIFO Buffers for adding the IWB. We use both two strategies to enhance FIFO Buffers. When the number of total entries is large, the enhanced FIFO Buffers perform better than a centralized instruction window.