具執行軌跡支援之x86指令流緩衝器

Abstract

現今的x86微處理機普遍採用超純量架構，只有提供高頻寬的指令流可以提昇超純量架構潛在的效能， 而提供高頻寬的指令流正是指令擷取器的工作。指令流緩衝器的目的是為了提供指令擷取器充裕的指令， 然而目前的指令流緩衝器受到了分支指令跟跨行指令的限制，使得每個時脈無法送出儘可能多的指令數。 在此篇論文中，我們設計了一個跟分支目標緩衝區（Branch Target Buffer）結合的指令流緩衝器，解決了 分支指令跟跨行指令所造成的限制，同時我們也考慮了分支目標緩衝區回應時間對於我們的設計所造成的 影響。我們將針對指令流緩衝器的寬度及深度進行模擬並選定合理值，然後用此設定值跟其它微處理機的 平均擷取率作比較。模擬結果顯示，具二條寬度為64位元組緩衝器的指令流緩衝器為適當的選擇。

Nowaday x86 microprocessors implement superscalar processing. The potential performance of superscalar microprocessors can only be exploited when fed by high instruction bandwidth. This task is the responsibility of instruction fetcher. The purpose of the instruction stream buffers is to provide sufficient instructions for fetcher. Current instruction stream buffers are constrained by the limitation of branch instructions and split-line instructions. We propose a design of improved instruction stream buffers, which is coupled with BTB, to deal with these problems. We also consider the influence of BTB response time on our design. We do the simulation to decide the width and depth of our instruction stream buffers and compare the average fetch rate of our design and other microprocessors. Simulation results suggest that instruction stream buffers with two 64-byte entries is the proper choice.