多晶片模組之可測試設計及測試策略

Abstract

本論文之目的是針對多晶片模組發展一套有效率之可測試設計及測試策略。在互補式金屬氧化半導體多晶片模組之內建式電流測試方法中，適當地分割電路為多個模組以便加入內建式電流感應器是權衡測試成本及測試正確性的一個重要關鍵。目前多數的電路分割方法是以統計分析的方式找出一個固定的臨界值來決定模組的大小。這些方法的缺點是缺乏彈性，因為電流測試方法是以測量具類比性質的電流做為判斷電路錯誤之依據而非以測量數位信號之方式來判斷電路之錯誤。我們提出了一個基於模糊推理的方法，以提供一個具有彈性的臨界值來決定內建式電流測試方法中電路模組的大小。實驗結果顯示我們所提出的方法的確能在內建式電流測試之電路分割設計空間中找出適當的模組大小。其次，我們也發展出一個簡單而有效的模式來預估部份可測試多晶片模組之錯誤涵蓋率。這個模式能夠充分反應多晶片模組中錯誤涵蓋率、測試方法，以及可測試晶片之比例及其分佈之關係。實驗結果顯示我們所提出的模式可以有效地預估部份可測試多晶片模組之錯誤涵蓋率，其誤差範圍在5%內。此模式可以協助多晶片模組設計人員有效地規劃可測試晶片之使用。此外，我們也提出了一個基於多頻率掃描之測試方法來偵測多晶片模組之靜態及動態錯誤。我們藉由變更部分邊界掃描細胞之設計，使同樣的邊界掃描細胞不但可以用在晶片階層之測試上，同時也可以用於模組階層之測試上。實驗結果顯示因加入測試電路所造成之面積多支及延遲時間可以減少。

The goal of this thesis is to develop efficient DFT (design for testability) and test strategies for MCMs (multichip modules) during their production and test processes. In CMOS MCMs, partitioning a circuit into modules before using a separate built-in current sensor for each module is key to balancing between test cost and test correctness of built-in current test. Most partitioning methods use statistic analysis to find a fixed threshold and then to determine the size of a module. These methods are rigid and inflexible since IDDQ (quiescent power supply current) testing requires the measurement of an analog quantity rather than a digital signal. We propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Experimental results show that our design approach provides a feasible way to exploit the design space of BICT partitioning. A simple and efficient model for designers to estimate the fault coverage of a partially testable MCM is also derived. This model reflects the relationship between fault coverage, test methodology, and the ratio and distribution of DFT dies (dies with testability features) in an MCM. Experimental results show that our model can efficiently predict the actual fault coverage of a partially testable MCM with less than 5% deviation. It indeed facilitates the designers to plan the use of DFT dies in MCMs in an efficient way.In addition, we propose a multifrequency scan based MCM test method which is closely associated with the mixed technologies of MCMs. This method can detect both static and dynamic faults. Furthermore, by introducing modified boundary scan cells, the same boundary scan cells which are used in chip level test can also be used in module level test. Experimental results show that the area overhead as well as the extra delay due to the addition of test circuits can be reduced.