防制閂鎖效應的佈局準則訂定及靜電放電保護用電源箝制電路之設計

Abstract

本論文可分成兩個部分，一是針對基體互補式金氧半(bulk CMOS)中防制閂鎖效應的佈局準則訂定，另一是新型靜電放電保護用的電源箝制電路之設計。藉由對防制閂鎖效應的瞭解，本論文利用互補式金氧半中寄生的矽控整流器(SCR)特性，設計出新型的靜電放電保護電路。本論文把原本在積體電路中是缺點的閂鎖效應變做成靜電放電防護技術中的優點。 在目前被廣泛採用的基體互補式金氧半技術中，由於其積體電路中會有先天性寄生的矽控整流器特性，它會引起所謂閂鎖效應而影響積體電路的正常功能。然而它是先天性存在基體互補式金氧半積體電路之中，所以是無法消除的，除非採用其他特殊的製造技術，但其製造成本會大幅增加。因此在基體互補式金氧半積體電路中通常是加入防護圈(guard ring)在佈局中來提升對閂鎖效應的防護能力以達到節省成本的目的。但是加入防護圈在佈局之中會造成晶片的面積增加，因此本論文提出一個有效的實驗方法來萃取更精簡的佈局準則來防制閂鎖效應以達到節省面積的目的。而為了進一步提升內部電路(internal circuit)對閂鎖效應的防護能力，一組額外的防護圈設計放置在輸出/輸入電路(I/O circuit)和內部電路之間也首次在實驗晶片上驗證。透過實驗晶片包含溫度效應的實際量測，一組精簡的佈局準則分別在0.5-μm SPTM non-silicide和0.35-μm SPQM silicide 基體互補式金氧半製程中證明可以有效節省晶片面積且同時提昇整個晶片的閂鎖效應防護能力。 除了積體電路內部寄生的閂鎖效應造成的問題之外，外在環境因素的靜電放電也常造成積體電路的損傷。本論文提出一個新型的低漏電電流二極體串(diode string)用來做為靜電放電保護用電源箝制電路。三種前人所提出之靜電放電保護用電源箝制電路的二極體串設計也同時做在同一個實驗晶片，來比較這個新設計的改良效果。這個新設計藉著加入一個NMOS-Controlled SCR (NCLSCR)在二極體串之上以幫助二極體串阻絕漏電電流，而二極體串將幫助NCLSCR提升holding voltage以避免發生閂鎖效應的危險。這整個新設計的holding voltage可以藉著在二極體串中的二極體數目來做近乎線性的調整以針對不同跨壓的電源箝制應用。在積體電路正常工作的情形下，這個新的設計只有極低的漏電電流；但在靜電放電情形之下，這個新的設計可以快速被導通來排放靜電放電之電流。實驗數據證明，這個新的設計可以承受超過八千伏特的人體放電模式之靜電放電測試。

There are two parts included in this thesis, which are both related to the parasitic SCR device in the bulk CMOS technology. In the first part, an efficient experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of the bulk CMOS IC's. The layout rules are extracted from the experimental test-chips with the latchup sensors and different drawing spacings. A new latchup prevention design with an additional internal double guard rings between I/O cells and the internal circuits is first investigated in the fabricated experimental test-chips. Through detailed experimental verification including temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-μm SPTM non-silicide and a 0.35-μm SPQM silicide bulk CMOS processes. In the second part, a new diode string with very low leakage current is proposed for using in the power supply ESD clamp circuits. Three previous designs of the cascaded diode strings used in the power supply ESD clamp circuits are also fabricated in the same test-chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the cascaded diode string, the leakage current of this new diode string with 6 cascaded diodes under 5-V (3.3-V) forward bias can be controlled below 2.1 (1.07) nA at a temperature of 125°C. The holding voltage of proposed new design with NCLSCR can be linearly adjusted by changing the number of the cascaded diodes in the diode string for the application among the power lines with different voltage level. From the experimental results, the ESD level of this proposed ESD clamp circuit is greater than 8kV in the Human-Body-Model ESD zapping.