快閃式記憶元件中熱載子注入導致的可靠性問題研究

Abstract

隨著快閃式記憶元件的小型化，熱載子效應及其衍生的可靠性問題便顯得日益重要。這些熱載子衍生的可靠性問題包括氧化層傷害、寫入/抹除循環的耐久度（Endurance）、擾動問題（Disturbance）、以及資料保存（Data Retention）等。在本論文中，吾人將針對堆疊式快閃式記憶元件所面臨的熱載子可靠性問題進行研究。 首先，吾人根據電荷平衡原理，探討浮動閘極的基本效應，並根據理論發展出一套新式的浮動閘極電壓計算模式，同時提供一個正確的決定元件中各電極與浮動閘極間的電容耦合係數的方法。再者，根據此一新的模式，吾人提出一精簡的電路模擬模式（SPICE Model），此模式可正確的模擬快閃式記憶元件的電壓電流特性。其次，吾人發展一套新式的氧化層傷害之萃取技術，此技術可決定通道熱電子寫入與源極FN抹除所產生之界面狀態（Nit）與氧化層電荷（Qox）的空間分佈。利用上述所得到的Nit與Qox，吾人首次成功地發展閘極電流退化模式。在此模式中，吾人提出：填滿電子的界面狀態將排斥注入的熱電子，導致熱電子注入機率下降；而氧化層電荷將影響熱電子注入的界面位能障壁。再者，針對源極FN抹除所導致的氧化層漏電流(SILC)與元件資料擾動問題，吾人也提出一新的分析方法。此方法有兩個顯著的特色：一為可分離氧化層缺陷充放電與氧化層正電荷或氧化層缺陷引發之順序穿隧對SILC與資料擾動的影響；另一為可求得各個氧化層微量漏電流（<10-20A）的分量。 在本研究中，吾人發現熱電子注入所產生的Nit是導致閘極電流退化的主要原因。此熱電子注入產生的Nit所導致的閘極電流退化也是造成快閃式記憶元件寫入特性退化的主要原因。除此之外，吾人也發現在低氧化層電場條件下，微量漏電流或快閃式記憶元件的資料擾動係由氧化層缺陷充放電所引起；而在高氧化層電場條件下，微量漏電流或資料擾動則是因正氧化層電荷或氧化層缺陷引發之順序穿隧所產生。

Hot carrier induced reliability issues have become increasingly important for miniaturized flash memory design. These reliability issues include hot carrier related issues, such as oxide damage, program/erase cycling endurance, disturbance, and data retention. In this dissertation, the hot-carrier injection induced reliability problems in stacked-gate flash memories is investigated. First, a new model based on the charge-balance theory was proposed to accurately calculate the floating gate voltage. Based on the new model, the method to determine the capacitive coupling coefficients and a compact SPICE model was developed. Then, an oxide damage characterization method was developed for simultaneously determining the lateral distributions of interface states (Nit) and oxide charges (Qox) under both channel-hot-electron programming bias and source FN erase bias stress conditions. According to the extracted profiles of Nit and Qox, a new gate current model was successfully developed for the first time by taking the hot-electron stress generated Nit and Qox into account. In this model, we suggest that Nit filled with electrons will serve as a new scattering center and reduce the hot-electron injection probability. The generated Qox is also introduced as an additional factor affecting the potential barrier at the Si-SiO2 interface. Moreover, the oxide-field dependent stress-induced leakage current (SILC) as well as its related disturbance on the source FN erased flash memory has been studied by using a new approach. The salient features of the method are two fold. One is that the individual contributions of SILC and disturbance due to either carrier charging/discharging in the oxide or positive charge-assisted/trap-assisted tunneling (PCAT/TAT) of electrons into the floating gate can be separated. The other one is that it is very sensitive to determine the ultra-low SILC (< 10-20 A). In this study, we first observed that the generated Nit dominates the gate current degradation not only at the IB,max stress condition but also at the IG,max stress condition. The major programming degradation mechanisms of flash memory cells after P/E cycles due to Nit was also identified. In addition, we also observed that the carrier charging/discharging in the oxide is the main disturb mechanism at low oxide field. At high oxide field, PCAT/TAT of electrons into the floating gate is the major cause for the disturb failure.