1.25 Gbps CMOS 數位發射機

Abstract

本篇論文描述一個 3.3 伏特, 每秒能發射 1.25 兆位元的 CMOS 數位發射機,它包含有十個相位的相鎖迴路時脈產生器, 十對一多工器, 以及一能驅動50歐姆的輸出驅動器. 此系統在此的主要應用於高速串列傳輸, 把 125 MHz 10 位元的並列資料, 轉換成串列資料. 十個相位的相鎖迴路時脈產生器是本論文的核心, 由電壓控制振盪器, 相位/頻率偵測器和電荷充放式濾波器所組成,且加入一相位平均化電路, 能減小相位誤差, 故能產生 10 個規則排列的精確相位, 且平均分佈於一個週期內, 壓控振盪器是從 0.2 MHz 到 250 MHz, 中心頻率為 125 MHz. 此相鎖迴路系統是使用 0.35mm 1P4M CMOS 製程技術下線生產. 電源電壓為 3.3V, 整個面績為 1800×1800 mm2, 消耗功率約 160 mV.

This thesis described the design of a 3.3 V CMOS digital transmitter that transmits 1.25 gigabit per second, which is composed of a 10 phase phase-lock-loop(PLL) clock generator, a 10 to 1 multiplexer and an output driver which drives 50 ohm. The digital transmitter is used in the high speed serial link which converts parallel data into serial data. The 10 phase PLL clock generator is composed of a voltage-controlled oscillator(VCO), a phase/Frequency Detector(PFD), a charge pumping filter(CP), and a phase average circuit, due to minimize phase jitter. The PLL generates 10 outputs with equally-spaced phases spanning the entire oscillation period. The ouput frequency of the VCO varies from 0.2 MHz to 250 MHz, and the central frequency is 125 MHz. The digital transmitter has been fabricated with a 0.35mm 1P4M CMOS technology. Total power consumption is about 160 mW under a 3.3 V supply.