完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wong, Cheng-Chi | en_US |
dc.contributor.author | Tang, Cheng-Hao | en_US |
dc.contributor.author | Lai, Ming-Wei | en_US |
dc.contributor.author | Zheng, Yan-Xiu | en_US |
dc.contributor.author | Lin, Chien-Ching | en_US |
dc.contributor.author | Chang, Hsie-Chia | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.contributor.author | Su, Yu-T. | en_US |
dc.date.accessioned | 2014-12-08T15:08:26Z | - |
dc.date.available | 2014-12-08T15:08:26Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-0786-6 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/6523 | - |
dc.description.abstract | This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver | en_US |
dc.type | Article | en_US |
dc.identifier.journal | PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE | en_US |
dc.citation.spage | 273 | en_US |
dc.citation.epage | 276 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000252233200062 | - |
顯示於類別: | 會議論文 |