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dc.contributor.authorWong, Cheng-Chien_US
dc.contributor.authorTang, Cheng-Haoen_US
dc.contributor.authorLai, Ming-Weien_US
dc.contributor.authorZheng, Yan-Xiuen_US
dc.contributor.authorLin, Chien-Chingen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.contributor.authorSu, Yu-T.en_US
dc.date.accessioned2014-12-08T15:08:26Z-
dc.date.available2014-12-08T15:08:26Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0786-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/6523-
dc.description.abstractThis paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.en_US
dc.language.isoen_USen_US
dc.titleA 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaveren_US
dc.typeArticleen_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage273en_US
dc.citation.epage276en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000252233200062-
顯示於類別:會議論文