A 2.5 Gbps CMOS fully integrated optical receicer with lateral PIN detector

Abstract

This paper presents the design of a monolithically integrated CMOS optical receiver, including a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. The optical receiver is capable of delivering 420 mV(pp) to 50 Omega output load and operating up to 2.5 Gbps without an equalizer. Implemented in a generic 0.18 mu m CMOS technology, the total power dissipation is 138 mW. The chip size is 0.53 mm(2).