用於十六倍速數位多功能光碟讀取通道晶片之類比/數位轉換器

Abstract

本篇論文描述一個6位元、每秒430百萬次取樣的全差動類比/數位轉換器。此轉換器係使用於十六倍速數位多功能光碟讀取通道晶片上。由於數位多功能光碟通道信號連續不斷的輸入，因此自動歸零(auto-zeroing)必須在背景中執行，我們在電路中加入一個額外的比較器以達成在背景自動歸零的目的。此外，我們並利用一個鎖相迴路產生此類比/數位轉換器所需的轉換時脈。本論文中，我們亦詳細地討論使類比/數位轉換器效能降低的一些非理想效應。模擬結果顯示此類比/數位轉換器在160百萬赫茲的輸入頻率及500百萬赫茲的取樣頻率下能夠達到5.57的有效位元數。使用0.35微米雙層複晶矽互補金氧半製程，我們所設計的類比/數位轉換器可在3.3伏特的電源下工作，並達到500百萬赫茲的取樣頻率，而其消耗之功率約為200毫瓦。

In this thesis describes a 6 bit, 430Msample/s fully differential analog-to-digital converter (ADC) that performs the conversion to meet the requirement for the 16XS DVD read channel chip. Owing to the continuous input of DVD channel signal, auto-zeroing should be done in background. In this regard, one additional comparator is added for background auto-zeroing. In addition, a high performance phase locked-loop (PLL) is used for generating conversion clock of the ADC. Moreover, some nonideal effects that degrade the performance of the ADC are also discussed in detail. Simulation results show that the converter can achieve effective number of bits higher than 5.5 at the input frequency up to 160MHz and sampling frequency up to 500MHz. Using 0.35μm DPTM CMOS process, the converter consumes 200mW at 3.3V when running at 500MHz. 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 HIGH SPEED ADC ARCHITECTURES 5 2.1 FLASH ADC ARCHITECTURE 5 2.2 TWO-STEP ADC ARCHITECTURE 6 2.3 FOLDING ADC ARCHITECTURE 7 2.4 PIPELINED ADC ARCHITECTURE 8 CHAPTER 3 A 6-BIT FLASH ADC ARCHITECTURE 10 3.1 CONVENTIONAL AUTO-ZEROING OPERATION 10 3.2 INTERLEAVED AUTO-ZEROING OPERATION 11 3.3 ADC ARCHITECTURE AND BACKGROUND AUTO-ZEROING OPERATION 12 CHAPTER 4 CIRCUIT DESIGN AND SIMULATIONS 21 4.1 INPUT BUFFER 21 4.2 REFERENCE VOLTAGE GENERATION 23 4.3 PHASE-LOCKED LOOP 25 4.3.1 PLL architecture 25 4.3.2 Phase frequency detector 26 4.3.3 Charge pump and loop filter 27 4.3.4 Voltage-controlled oscillator 29 4.4 COMPARATOR CIRCUIT 32 4.4.1 Preamplifier circuit 35 4.4.2 Latch circuit 38 4.5 ENCODER 39 4.5.1 Error detection and correction 40 4.5.2 Encoding 40 CHAPTER 5 NONIDEAL EFFECTS 43 5.1 RESISTOR STRING DEVIATION 43 5.2 CLOCK JITTER 47 5.3 CLOCK AND SIGNAL SKEW 49 5.4 POWER SUPPLY BOUNCE INDUCED EFFECT 56 CHAPTER 6 TESTING OF ADC 59 6.1 DECIMATION APPROACH 59 6.2 DECIMATION TESTING CIRCUIT 61 CHAPTER 7 LAYOUT AND SIMULATION RESULTS 63 7.1 POWER SUPPLY PARTITION 63 7.2 FLOORPLAN 65 7.3 SIMULATION RESULTS 67 CHAPTER 8 CONCLUSION AND FUTURE WORK 70